<karenw>
Yay, I finally managed to give limine the metaphorical boot and escape needing to keep it in memory.
<karenw>
And bonus points, zeroing all free memory to see if I missed keeping anything important *didn't* crash. (As a negative test I marked the stack as free and it does indeed crash with a return to NULL)
<heat>
note: don't actually do that
<heat>
it's problematic at least in virtual machines because it actually commits the vm's memory
<karenw>
Yeah, I removed it. (If I kept it, it would be behind some debugging flag or something)
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<geist>
yah to this day i'm annoyed there's not a solid way to get linux to just zero out all the ram it's not using.
<geist>
you can ell it to dump the FS cache but it just frees the ram to the pmm. since there's no background page zeroer anymore, you can't even kick it to do that
<geist>
so that the VMM can dedup the zero pages
<geist>
or for that matter some sort of concept of 'TRIM' for VMs would be nice
<geist>
like 'i'm not using this page, remove it from my mapping'
<geist>
but i havne't seen anything like that in any of the paravirtualization schemes, aside from maybe balloons but those are VMM driven, not guest driven
<geist>
unless there's a piece i'm missing there
<karenw>
Ah yes, that feeling when you turn optimizations on and everything explodes. (I didn't mark written-by-bootloader globals as __attribute__((used)) and they got assumed to be always 0)
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<geist>
ah fun. that's one i hadn't thought about
<geist>
and/or they would get moved into BSS, which i remember when gcc 4 or so did that and it broke so much code
<geist>
there's a command line switch to disable that particular feature. any globals/statics that are not initialized leave in .data
<clever>
ive done something similar and never had problems, but i was forcing the struct into a special section
<clever>
the previous stage looked for that section specifically, and patched whatever was at the start of the section
<clever>
oh, and one field had to contain a magic#, so it wasnt entirely un-initialized
<kof673>
> the default system compiler for RHEL7 is gcc 4.8 /me whistles nervously, paranoidly glancing at # mips-unknown-elf-gcc-4.8.5 # nestedvm 2021 06 26 # mips-jsmips-gcc-4.5.1
<kof673>
the "E" is for enterprise, so for the right price, i think they even support a version back or two of the "official"
<kof673>
(i.e. IBM support, and whoever else)
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<kof673>
nikolar, pcc (portable c compiler, the revival, following from cvs circa 2017) how many of those actually work is another story, some are likely just there because the "original" pcc had them : > arch/amd64 arch/hppa arch/m16c arch/mips64 arch/pdp11 arch/sparc64 arch/arm arch/i386 arch/m68k arch/nova arch/pdp7 arch/superh arch/i86 arch/mips arch/pdp10 arch/powerpc arch/vax
<kof673>
m68k was presumably working at some point in pcc history :D
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<kof673>
it doesn't like my "modern" knoppix 8.1 headers, nor however system crt*.o files are laid out/names: pcc -D_IO_STDIO_H -D_STDIO_H -S hello.c -o hello.s then just use gcc to "link" from the asm it generates lol nwcc also does not like whataver crt file layout, but can be used in the same manner lol
<kof673>
i'll say circa 2017 "still works" on x86-32 linux at least lol
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<karenw>
My brain hurts trying to understand recusive paging. I doubt I actually want to implement it, but the fact I can't actually grok what's happening is making me doubt myself.
<karenw>
Like, why does qemu `info mem` report lots and lots of random read-only mappings in the lower half of the address space after I add a recursive map
<karenw>
*seemingly random
<Mutabah>
Fractal/recursive mappings are a trick that abuses the fact that (on x86) - A page directory entry looks very similar to a page table entry
<Mutabah>
So (for 32-bit two-level paging), if you set a PD entry to point back at itself, when that address range is accessed the PD is re-intepreted as a PT
<karenw>
So all I should have to do is `pml4_virt[511] = pml4_phy | PAGE_RW | PAGE_P` and they just work?
<Mutabah>
Yep
<karenw>
Then why does qemu interpret the newly set up pages and say there's 0x8000 bytes mapped at 0x0000631687000000? That's way below any address I expect the page tables to now show up.
<Mutabah>
Check the value in CR3, and the contents of the PML4 and make sure that they're sensible?
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<heat>
H E A T
<Ermine>
warmth
<kof673>
yes, yoga flame is part of the moves > Dhalsim's Yoga Teleport. Executed by performing a Shoryuken/reverse Shoryuken motion and pressing either all three punches or all three kicks
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<zid`>
It took me all day
<zid`>
but I finally finished writing this code wrong
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<Ermine>
now delete it right
<zid`>
need to modify it a bunch, I knew I was writing it wrong for what I ultimately wanted
<zid`>
but it was easier to finish, then test it
<zid`>
as an intermediate step
<zid`>
then convert it to what I did want
<geist>
yes, it is The Way
<geist>
write the code wrong, delete it, write a great version
<zid`>
(I'm returning a string of what I found to match, rather than metadata about the match)
<zid`>
but I wanted to get all the match rules working
<geist>
oh no! this sounds precisely like the sort of things that an AI will write and do better than you
<zid`>
if someone wants to try it, lmk
<geist>
well ust saying thingsl ike this i think they tend to do halfway decent at, since the spec can be fairly specified precisely
<zid`>
I mean, I could just throw the BNF into a generic tool, presumably
<zid`>
bison or whatever it is
<zid`>
the lexer generator
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<heat>
step 1: write code wrong
<heat>
step 2: never delete it
<heat>
step 3: incur technical debt and endless issues
<heat>
step 4: literally never do anything about it
<childlikempress>
BASED BASED BASED BASED BASED BASED BASED BASED
<geist>
step 5: job security
<Ermine>
I've read "endless issues" as "endian issues"
<heat>
retire and do consulting
<heat>
Ermine, that also works
<childlikempress>
i'm gonna be an endian when i grow up
<childlikempress>
there's gonna be little endian big endian and Mondenkind endian
<kof673>
i built that http://git.simple-cc.org "corrected" the missing i386 portions ...and then found only qbe backends work, the others will spit out asm like string data, but no code. luckil,y it can still generate x86-64 and run with qemu-x86_64 even, but need to build an x86-64 musl i suppose :/
<bslsk05>
git.simple-cc.org: Repositories
<kof673>
i was disappointed, proud, then...oh that's why it fails, non-qbe backends were never working in the first place probably
<nikolar>
kof673: wait does scc use qbe?
<kof673>
it has different backends, and you can spit out ir...so qbe takes the ir and makes asm
<kof673>
so "cc2" has qbe backends, arm64 and x86-64 IIRC
<kof673>
cc1 even has a z80, but same, just "string data" goes to the asm
<kof673>
you can literally just pipe from cc1 to cc2, as i found out troubleshooting
<kof673>
yes, and you the qbe git link is broke, so i just got a tarball and fixed the makefile to not use git lol
<nikolar>
so i guess you could also add an m68k backend to it :P
<kof673>
well i know nothing but the cc2 parts look very small actually, for someone who knows what they are doing
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<kof673>
> The current version of QBE can target amd64 (linux and osx), arm64, and riscv64 # i don't think there is any requirement of that, just noone has implemented others
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<nikolar>
as far as i know, a lot of qbe code internally assumes 64bit
<nikolar>
so no one has bothered to untangle that either
<netbsduser>
zid`: they're a community of people who invent new "minimalist" alternatives to popular software
<netbsduser>
of dubious import
<zid`>
but why name themselves 'crappy sword'
<netbsduser>
the most bizarre one is a webkitgtk-based web browser in "under 2000 lines of code" which of course depends on gtk+, webkit, etc
<heat>
right, but musl is also a "minimalist" community in many aspects, and isn't associated with suckless
<zid`>
I bet I could init gecko and gtk in 2k lines
<heat>
suckless is basically "what if unix so hard that it's impractical and bad and fascist"
<heat>
btw TIL autotest
<heat>
what if testing framework but GNU and using m4
<Ermine>
seems like it busyloops around some register state?
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<kof673>
i remember a browser like that a long time ago, but surely vanished, don't remember the name. seamonkey just disable things you don't want, was always "light enough" IMO
<_ngn_>
ive a question, on the wiki page for AHCI there are "signatures" for different device types, looking at the spec the signature just seems to be a combination of LBA high, mid, low and the sector count, however in the SATA spec none of these have a predefined value, so my question is how exactly these "signatures" are obtained?
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<Ermine>
What if I just spam 'em with what checkpatch.pl found out
<heat>
spam who?
<Ermine>
radeon maintainers
<heat>
do not
<heat>
sending patches fixing random checkpatch.pl crap is very frowned upon
<childlikempress>
heat is very frowned upon but ur still hot😘
<heat>
😳
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<geist>
_ngn: i found the AHCI/sata spec to be a bit annoying since it seems to just assume you understand the underlying ATA spec
<geist>
like AHCI has some amount of ATA baked into it in that it’s offloading some of the commands but error codes and some structures are part of ATA and not AHCI
<geist>
like it’s not just a simple transport for ATA, and it blurs the lines a bit by handling some of the layer above
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<heat>
yeah
<heat>
weird analogy but basically AHCI is to SATA what TSO is to tcp
<heat>
it's a fancy offload engine that kind of assume you know SATA properly
<Ermine>
what did tso do to tcp
<nikolar>
kek
<heat>
TSO is tcp segmentation offload
<heat>
NICs with TSO + GRO + whatever kinda speak TCP natively themselves, you just drive them
<heat>
my point being that AHCI offloads sata but you still need to know sata, just like TSO + GRO + wahtever offload TCP, but you still need to know TCP
<Ermine>
it's a pity that there's no kernel maintainers named gro
<heat>
sir, he's called T'so, not tso
<childlikempress>
theodore total 'store ordering
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<karenw>
Hi! So I'm looking at the various ways to specify caching behaviour on x86_64 and hoo boy am I confused. I assume that using the PAT is the correct method in 202x, but when should I use which type?
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<karenw>
And unlike the RW/US/XD bits, the PAT/PWD/PCD bits in page directories are NOT inherited and only apply to reading the next level of the page tables?
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<karenw>
I'm guessing most RAM should be WB, I/O should be UC- and the framebuffer should be WC? And I just leave the MTRRs as the firmware left them?
<_ngn>
geist: but theres also no predefined value in the ATA spec (i looked for it in ACS-3) is there any other spec that i need to check?
<heat>
look in the SATA spec. but this might be One Of Those Things that's spread out across various specs like ATAPI and shit
<heat>
karenw, >I assume that using the PAT
<heat>
technically yes, practically the firmware sets up the MTRRs for you (and those combine/override the PAT)
<heat>
but in theory you want to use them, yes
<heat>
>but when should I use which type?
<karenw>
Yeah, that's why I mentioned UC- (so the MTRRs can override it) vs UC (which overrides the MTRRs)
<heat>
RAM is WB, IO is either UC or UC- (can't remember the difference), framebuffers and various other gpu memory and shit is usually WC
<heat>
right, if that's the difference then yeah, you have it right
<heat>
>the PAT/PWD/PCD bits in page directories are NOT inherited
<heat>
honestly i don't know, but you don't need to set those bits
<heat>
i suspect you're right because i distinctly recall CR3 having similar bits for that