sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<clever> lets say that the core-local irq 7 and 9 are both pending and enabled, and i unmask irq's, which one does the standard say the cpu should service first?
<jrtc27> 7
<jrtc27> privileged spec assigns a static order on the interrupt identities defined by the spec
<clever> is it more complex then just closer to 0 being higher priority?
<jrtc27> yes
<jrtc27> external, then software, then timer
<jrtc27> machine before supervisor
<clever> ah
<jrtc27> see the mip/mie section in the priv spec
<jrtc27> towards the end
<clever> so i cant just find the first set bit, and go with that
<clever> jrtc27: ah yep, i see, it says that the priority is fixed for simplicity
<smaeul> see also section 5.1 of the AIA spec
<clever> it also looks like 7 and 9 is a bit mixed up
<clever> 7 is machine timer, while 9 is supervisor external
<clever> i think i want 7 and 11 instead
<sorear> it's unclear how much license implementations have to have nonzero latency for interrupts, make states where an interrupt could be taken but hasn't yet visible, etc
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<clever> software interrupts not implemented currently
<clever> i'm not even sure supervisor mode is implemented
<sorear> > Is "incomplete" in that it didn't implement the tons of the spec that Linux doesn't (and you shouldn't) use.
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<clever> jrtc27: oh, i notice a minor problem in terms of how irq's are handled, the emulator only checks the irq state after executing 1024 opcodes
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<drmpeg> Ubuntu 24.04 works very nicely on the VF2.
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