18:39 <Peanut> Litex seems unhappy with my Meson - I have 0.60.3 installed (through pip3), but check_meson in litex/soc/integration/builder.py still is unable to find it.

18:40 <Peanut> Any hints?

18:42 <Peanut> Oh wait, it's building now ($PATH was not pointing to the right directory)

18:48 <Peanut> Almost there now - 'INFO:SoC:Auto-Resizing ROM rom from 0x200000 to 0x7cc4", and then "Failed to open input file". Trying to build a SoC for the Butterstick ECP5 board.

18:50 <Peanut> The file 'gsd_butterstick.bit' is missing.

18:53 <nickoe> What toolchain is to be used for the butterstrick? @ Peanut

18:53 <nickoe> Do you have some more log context?

18:53 <nickoe> What is the exact command you use to build it?

18:54 <Peanut> The second one is the easier to anser: ./gsd_butterstick.py (from https://github.com/butterstick-fpga/litex-examples )

18:55 <Peanut> https://github.com/butterstick-fpga/litex-examples/blob/main/soc_example/gsd_butterstick.py

18:55 <Peanut> :244

18:56 <Peanut> It fails at the very last stages, making the dfu - I think that the file 'config' doesn't get made or exist.

18:57 <Peanut> Yup, the config file is missing, should be at 'litex-examples/soc_example/build/gsd_butterstick/gateware/gsd_butterstick.config'

18:58 <gatecat> are there any errors or anything happening before that ?

18:59 <Peanut> No, it seems to build the SoC perfectly. It's just that ecppack fails due to '--input {config}' failing, as the config file in question is not there.

18:59 <gatecat> are you using trellis ?

19:00 <Peanut> Yes, trellis/nextpnr-ecp5

19:01 <gatecat> yeah, that all sounds fine, perhaps the problem is something in litex has changed the name of the file that's being generated

19:01 <gatecat> is there a '.config' file of any name inside the build folder ?

19:02 <Peanut> No, I've already searched for \*.config

19:02 <gatecat> what are the last lines of output before it fails ?

19:03 <Peanut> "INFO:SoC:Initializing ROM rom with contents (Size: 0x7cc4).", "INFO:SoC:Auto-Resizing ROM rom from 0x20000 to 0x7cc4."

19:03 <Peanut> That's building the BIOS.

19:03 <gatecat> sounds like it's not running yosys and nextpnr

19:03 <gatecat> oh, can you try running it with --build

19:04 <Peanut> Oh yes, CPU fan just kicked in - this is probably going to take a while.

19:09 <Peanut> Actually that went quite fast, now I just need to figure which dfu-util target to use.

19:18 <Peanut> Wow, working RiscV SoC, running Linux, in maybe two hours of tinkering, this is very impressive, thanks!

19:21 <gatecat> yay \o/

19:21 <gatecat> glad it's working :D

19:50 <Peanut> Seems I spoke a bit too soon - where can one find images/boot.json or images/boot.bin? Is that supposed to be generated as well?

19:57 <gatecat> I think this would only be generated if you built some software to run

19:58 <gatecat> https://github.com/enjoy-digital/litex/tree/master/litex/soc/software/demo should be able to create an example boot.bin for test purposes

20:02 <Peanut> Ah, I see - I thought the next stage would be booting Linux, but we're clearly still some distance away from that.

20:19 <Wolfvak> You can use the linux-on-litex-vexriscv repo, they have prebuilt kernels

20:33 <Peanut> Wolfvak: they mention they have prebuilt bitstreams, but I haven't found the kernels/rootfs/opensbi yet?

20:55 <hubmartin> Hi, I'm having some issues of porting LiteX to Lattice ECP5 VIP processor board. I have added SPI FLASH support but when I enable DDR3, the bitstream works (LED chaser works) but the new BIOS does not output anything on UART. When I load older BIOS without the DDR3 support (but with the new DDR3 bitstream) the BIOS starts correctly. Wehn I compare

20:55 <hubmartin> the objdump of ELF bios files, the linker addresees points correctly to SPI flash.. https://github.com/hubmartin/litex-lattice-ecp5-vip

20:55 <hubmartin> Now I made it work when enjoy-digital on twitter https://twitter.com/hubmartin/status/1475195655312322560 suggested to disable SPI FLASH and keep BIOS in the BRAM.

20:55 <hubmartin> So it seems like ther is some issue with BIOS linking/compiling. Because with new bitsream SPI FLASH+DDR3 the old BIOS firmware works (of course, without DDR3 because there is no FW support)

20:55 <hubmartin> Thanks for any hints.

21:02 <Wolfvak> Peanut, they're in a pinned issue

21:02 <Wolfvak> https://github.com/litex-hub/linux-on-litex-vexriscv/issues/164

21:04 <Peanut> *lol* thanks. That's going to be useful, because I've just done the whole 'buildroot thing', but it barfs with 'Incorrect selection of kernel headers: expected 5.15.x, got 5.14.x'. So a prebuilt Linux filesystem is a great help, thanks.

21:12 <Peanut> "Received firmware download request from device, uploading image, upload calibration, Upload to device failed due to data corruption (CRC error)."

21:12 <Peanut> So it uploads Image correctly, but it seems to fail a CRC check.

21:13 <Peanut> Or possibly it fails on a missing rv32.dtb, that's the next file to get.

21:21 <Peanut> Making rv32.dtb (./make --board=butterstick) requires sbt, which would require installing scala and java?

21:31 <Wolfvak> yes

21:31 <Wolfvak> you want to do "./make --board=butterstick --build", that way you get the bitstream and bios

21:31 <Wolfvak> the kernel itself and opensbi are precompiled from that issue

21:32 <Peanut> OK, just asking because I've already built a working SoC bitstream.

21:32 <gatecat> that SoC example is probably intended as a standalone SoC and not linux-compatible

21:34 <Peanut> Ah, ok. Well, that should keep me busy for a bit again :-)

21:34 <Peanut> The Butterstick doesn't have a prebuilt image yet.

21:50 <Wolfvak> since it's an 85F device you might even be able to fit Rocket or multiple VexRiscv cores

21:50 <nickoe> Anyone who knows why I can't boot the demo app with --sdram --sdram-init boot.json?

21:51 <nickoe> But it works when loading via lxterm and the crossover uart.

21:51 <Peanut> Wolfvak: Likely - the Soc I built earlier only uses like 21% of the device. Would be fun to have a dual core, but I have other plans with it.

23:05 <Peanut> Meh.. so I think I have a Linux compatible SoC now. It builds, runs fine, but doesn't seem to have the serial-over-usb.