_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<Peanut> Litex seems unhappy with my Meson - I have 0.60.3 installed (through pip3), but check_meson in litex/soc/integration/builder.py still is unable to find it.
<Peanut> Any hints?
<Peanut> Oh wait, it's building now ($PATH was not pointing to the right directory)
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<Peanut> Almost there now - 'INFO:SoC:Auto-Resizing ROM rom from 0x200000 to 0x7cc4", and then "Failed to open input file". Trying to build a SoC for the Butterstick ECP5 board.
<Peanut> The file 'gsd_butterstick.bit' is missing.
<nickoe> What toolchain is to be used for the butterstrick? @ Peanut
<nickoe> Do you have some more log context?
<nickoe> What is the exact command you use to build it?
<Peanut> The second one is the easier to anser: ./gsd_butterstick.py (from https://github.com/butterstick-fpga/litex-examples )
<Peanut> :244
<Peanut> It fails at the very last stages, making the dfu - I think that the file 'config' doesn't get made or exist.
<Peanut> Yup, the config file is missing, should be at 'litex-examples/soc_example/build/gsd_butterstick/gateware/gsd_butterstick.config'
<gatecat> are there any errors or anything happening before that ?
<Peanut> No, it seems to build the SoC perfectly. It's just that ecppack fails due to '--input {config}' failing, as the config file in question is not there.
<gatecat> are you using trellis ?
<Peanut> Yes, trellis/nextpnr-ecp5
<gatecat> yeah, that all sounds fine, perhaps the problem is something in litex has changed the name of the file that's being generated
<gatecat> is there a '.config' file of any name inside the build folder ?
<Peanut> No, I've already searched for \*.config
<gatecat> what are the last lines of output before it fails ?
<Peanut> "INFO:SoC:Initializing ROM rom with contents (Size: 0x7cc4).", "INFO:SoC:Auto-Resizing ROM rom from 0x20000 to 0x7cc4."
<Peanut> That's building the BIOS.
<gatecat> sounds like it's not running yosys and nextpnr
<gatecat> oh, can you try running it with --build
<Peanut> Oh yes, CPU fan just kicked in - this is probably going to take a while.
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<Peanut> Actually that went quite fast, now I just need to figure which dfu-util target to use.
<Peanut> Wow, working RiscV SoC, running Linux, in maybe two hours of tinkering, this is very impressive, thanks!
<gatecat> yay \o/
<gatecat> glad it's working :D
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<Peanut> Seems I spoke a bit too soon - where can one find images/boot.json or images/boot.bin? Is that supposed to be generated as well?
<gatecat> I think this would only be generated if you built some software to run
<gatecat> https://github.com/enjoy-digital/litex/tree/master/litex/soc/software/demo should be able to create an example boot.bin for test purposes
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<Peanut> Ah, I see - I thought the next stage would be booting Linux, but we're clearly still some distance away from that.
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<Wolfvak> You can use the linux-on-litex-vexriscv repo, they have prebuilt kernels
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<Peanut> Wolfvak: they mention they have prebuilt bitstreams, but I haven't found the kernels/rootfs/opensbi yet?
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<hubmartin> Hi, I'm having some issues of porting LiteX to Lattice ECP5 VIP processor board. I have added SPI FLASH support but when I enable DDR3, the bitstream works (LED chaser works) but the new BIOS does not output anything on UART. When I load older BIOS without the DDR3 support (but with the new DDR3 bitstream) the BIOS starts correctly. Wehn I compare
<hubmartin> the objdump of ELF bios files, the linker addresees points correctly to SPI flash.. https://github.com/hubmartin/litex-lattice-ecp5-vip
<hubmartin> Now I made it work when enjoy-digital on twitter https://twitter.com/hubmartin/status/1475195655312322560 suggested to disable SPI FLASH and keep BIOS in the BRAM.
<hubmartin> So it seems like ther is some issue with BIOS linking/compiling. Because with new bitsream SPI FLASH+DDR3 the old BIOS firmware works (of course, without DDR3 because there is no FW support)
<hubmartin> Thanks for any hints.
<Wolfvak> Peanut, they're in a pinned issue
<Peanut> *lol* thanks. That's going to be useful, because I've just done the whole 'buildroot thing', but it barfs with 'Incorrect selection of kernel headers: expected 5.15.x, got 5.14.x'. So a prebuilt Linux filesystem is a great help, thanks.
<Peanut> "Received firmware download request from device, uploading image, upload calibration, Upload to device failed due to data corruption (CRC error)."
<Peanut> So it uploads Image correctly, but it seems to fail a CRC check.
<Peanut> Or possibly it fails on a missing rv32.dtb, that's the next file to get.
<Peanut> Making rv32.dtb (./make --board=butterstick) requires sbt, which would require installing scala and java?
<Wolfvak> yes
<Wolfvak> you want to do "./make --board=butterstick --build", that way you get the bitstream and bios
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<Wolfvak> the kernel itself and opensbi are precompiled from that issue
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<Peanut> OK, just asking because I've already built a working SoC bitstream.
<gatecat> that SoC example is probably intended as a standalone SoC and not linux-compatible
<Peanut> Ah, ok. Well, that should keep me busy for a bit again :-)
<Peanut> The Butterstick doesn't have a prebuilt image yet.
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<Wolfvak> since it's an 85F device you might even be able to fit Rocket or multiple VexRiscv cores
<nickoe> Anyone who knows why I can't boot the demo app with --sdram --sdram-init boot.json?
<nickoe> But it works when loading via lxterm and the crossover uart.
<Peanut> Wolfvak: Likely - the Soc I built earlier only uses like 21% of the device. Would be fun to have a dual core, but I have other plans with it.
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<Peanut> Meh.. so I think I have a Linux compatible SoC now. It builds, runs fine, but doesn't seem to have the serial-over-usb.
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