00:13 <jevinskie[m]> Ok time to do some fpga stuff again, it’s been too long. I’ll be trying to merge the useful bits of this to litex mainline :) https://pbs.twimg.com/media/FKANoSaUYAAl_BV?format=jpg&name=large

00:14 <jevinskie[m]> What’s the policy on migen patches? Have to get them upsteamed first?

00:18 <jevinskie[m]> First order of business will be altera JTAGbone. It seems to be broken from a simple copy-pasta from that old branch so time to use ol’ reliable uartbone and litescope to debug the TAP FSM. Here’s the code so far, I hope it’s not too far off from mergable standards :) https://github.com/jevinskie/litex/commit/8e1c68fd45ec49d05d67cc6c2cf09563fb0f8e0a

08:03 <_florent_> jevinskie[m]: Nice work on the SPI Flash Emulator, this could be useful for lots of things (even for FPGA development)!

08:05 <_florent_> jevinskie[m]: We could indeed start merging your JTAGBone support for Altera. I'm happy reviewing/adapting the code a bit while merging, I'll just also need a way to reproduce it (if you could do a PR for one Altera board and provide the commands you are using).

11:22 <acathla> _florent_, the default target for the ice40up5k_evn freezes trying to enable SPI quad mode (in BIOS) and takes 3741LC, if I add "with_master=False" to the SPI flash initialization parameters it works fine and takes 3440 LC

11:24 <acathla> (I'm trying to make spiflash work again after updating LiteX)

11:38 <acathla> How can I add bitbang spi to LiteSPI now?

15:07 <_florent_> acathla: bitbang is not supported yet in LiteSPI, if you want to use the functionalities of the old SPI Flash core, you can copy it in your project and just reintegrate it in your target

17:15 <jevinskie[m]> _florent_: Thanks! I'll provide instructions in the eventual PR but I think it should mostly Just Work once I add the openocd config file generation for USB Blasters (I also have examples for using an openocd-only flow if that's of interest, lets you use something like a FTDI dongle instead of a blaster, if that is of interest). I'll add support for the DECA in the PR since A) I know you have one as well B) with no built-in usb-serial

17:15 <jevinskie[m]> adapter, Atlantic JTAG UART is painfully slow and JTAGbone + crossover UART is far superior. :)

17:21 <jevinskie[m]> _florent_: I figured out my issue when I cherry-picked the JTAG changes to top of trunk. It was missing my migen modification to allow for FSM ongoing states to reset to non-zero (needed for the TEST_LOGIC_RESET ongoing signal). See the 4 line change in the link. For migen changes, do you want to get it upstreamed to the migen repo first? I've noticed you've avoided forking it so far. My other thought was some surgical monkey-patching to fix

17:21 <jevinskie[m]> up/enhance a couple of methods (the new approach I'm taking). https://github.com/jevinskie/migen/commit/f9bd7241c8d3cc534154fe762fa8e941bc8011af#diff-dc256a57d35c9990bef2595d62dbb024e2aacdd48692e18f2c91d502c5f58045R232-R236

17:21 <jevinskie[m]> Don't be afraid, the "iffy" modifications were other parts of that commit. ;-)

18:36 <acathla> _florent_, I did that first, it builds but does not boot. I don't know yet what's the problem.

19:35 <jevinskie[m]> Good, the JTAG issue was the lack of my migen FSM patch. Hmm I guess I can just make a ResetFixedFSM wrapper around FSM instead of monkey patching migen. Some of my other changes like signal naming enhancements can’t be done that way though.

22:17 <jevinskie[m]> Here are the Altera JTAG PRs: https://github.com/enjoy-digital/litex/pull/1188 https://github.com/litex-hub/litex-boards/pull/341

22:22 <jevinskie[m]> Time to clean up the Altera MII/RGMII work now :)