<_florent_>
This should allow you to see if the FPGA receives CGS correctly and then the ILAS
<_florent_>
and if ILAS is not the one expected, know where it is different
<_florent_>
yootis: I'm also waiting for the Titanium FPGAs with SerDes, it will be interesting to compare it to Xilinx's 7-Series and could be more interesting on some designs
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<_florent_>
tnt: Thanks for the PRBS PRS, I merged them but did minor changes:
<_florent_>
RX errors saturation is now disabled by default
<tnt>
Ack. I just didn't want to unexpectedly change the default behavior.
<tnt>
mmm ... how can you access the clock domain from a sub module ? I tried `self.adrv0_jesd.clock_domains.cd_jesd` and in the 'adrv0_jesd' module __ini__, I have a `self.clock_domains.cd_jesd = ClockDomain()` so I would have thought it'd be valid.
<tnt>
nm ... `self.adrv0_jesd.cd_jesd` it is. However the LiteScope analyzer want a string, not a clock domain object. I used .name hopefully that works.
<tnt>
It doesn't :/ Because name is just 'jesd' but given there is several it gets renamed to 'adrv0_jesd_jesd' during elabortation.
<_florent_>
tnt: In litescope, just put self.adrv0_jesd.cd_jesd.clk / self.adrv0_jesd.cd_jesd.rst signals
<tnt>
_florent_: ?
<_florent_>
tnt: Sorry, do you want to observe the clk or use it for capture?
<tnt>
Use it for capture.
<tnt>
Damn ... I crashed the host :/
<tnt>
Not sure how that happenned.
<_florent_>
ok, so what you can do is put a dummy string, the build will fails and display the available clock domains.
<tnt>
yeah, I ended up hardcoding the right string, but I was wondering if there was a way to "do it right" :)
<tnt>
I guess looking a tthe source of litescope, I could check if it's a ClockDomain and act accordingly.
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<tnt>
_florent_: does litejesd support having the GTH with data_width=40 ? i.e. 122.88 MHz "user clock" (cd_jesd) and a 4.9152G linerate
<_florent_>
tnt: it should, but I think I only used data_width=20 with RFICs (I was using 40-bit with another DAC).
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<tnt>
Mmm, I can't even get past CGS. Once in a while, one of the lane will get it but the other have just the same repeating data that's not the right char.
<tnt>
but if I enable the PRBS gen, I'll see all the lane data swtiching. And if I enable the PRBS checker (thought a modified test_prbs.py that uses the jesd_phy instead of the serdes0 CSRs), it works, PRBS check passes.
<tnt>
Mmm ... It just not aligning to K28.5
<tnt>
Looking at the raw output from GTH4, I see them, but with random alignements.
<tnt>
I'm not actually sure how this is supposed to work TBH. Is the GTH supposed to handle that internally ?
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<tnt>
I'm starting to seriously doubt gth_ultrascale.py ...
<tnt>
There is nothing in there related to the comma alignement that I can see, contrary to gt{p,x}_7series.py
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<SpaceCoaster>
The snickerdoodle support needs to have a XCI file for the ps7 description. The other zynq projects store it in GitHub litex-boards/files. Not sure how that works. For now I will put it in an AWS S3 bucket.
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<tnt>
Ok, I managed to properly (well, I think) enable comma detection and alignement logic on the GTH and now, it gets through CGS and gets to ILAS.
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<tnt>
_florent_: Mmm, I'm not sure how the ILAS checker is supposed to work. It seems no matter the phy data width, this get adapted during CDC to 32 bits. But if the phy data width was 20 bits, that means it takes 2 cycles to get a new 32 bit word. And I don't see where the ILAS checkers handles that.
<tnt>
You can see it matches 0302011C just fine. But then the next one 07060504 only comes in 2 cycles later off the phy but the ILAS checker expects it immediately, doesn't find it and resets the FSM.