_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> nickoe: litex_sim only supports binary files for now, I have some work planned to uniformizie targets/sim prameters in January and will add support for it while doing this
<Peanut> nickoe: Thanks - somewhat similar issue here, but I think that the Butterstick needs the Valentty/Luna-ACM USB driver, and perhaps some PLL and other settings.
<nickoe> _florent_: Ok, so "part 2" is definitely another issue then. I forgot to link to the issue last night for context: https://github.com/enjoy-digital/litex/issues/1142
<nickoe> _florent_: Is there anything else I shold try with litex_term and the fact that it works with --safe mode?
<nickoe> I would be really nice to unify the interfaces, I mean that is sorta "expected" since it already is that uniform and flexible at this point.
<nickoe> :)
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<Peanut> Managed to boot Linux on the OrangeCrab, that's a bit further along than the Butterstick.
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<nickoe> mm, sometimes I accidently offset single signals in gtkwave... how do I even do that and how do I reset it?
<tnt> nickoe: edit timewarp unwarp all
<nickoe> tnt: thanks!
<nickoe> What is the shortcut to do a single signal warp?
<tnt> I think it's like some modifier key and the mouse.
<Peanut> Just did "./make.py --board=orangecrab --build --with-rvc" - but the resulting core still reports itself as rv32ima, not rv32imac ?
<Peanut> (from /proc/cpuinfo, and OpenSBI)
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<nickoe> tnt: it is control + mouse drag on the graph