_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tcal> tnt: to follow up, I dug out another iCEBreaker board, uploaded the same bitstream, and it worked 100% including tty. So I think the board I was using could have degraded somehow (admittedly, I'm pretty casual about leaving boards lying about my desk among the clutter)
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<tnt> tcal: are both board the same revision ?
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<tcal> yep -- v1.0e. The old one *used* to work as expected, so whatever the flaw is, it snuck in in the last couple of months.
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<tnt> tcal: you can try iceprog -Q in case some bitstream set the QE=0 non-volatile bit ...
<tnt> On another subject: How does one deal with conflict in the CSR namespace :/ I have a custom i2c module with CSR and that prevents /libbase/i2c.c to build because the CSR_I2C_* values are the ones from my block and not the one from the default block (which I don't use).
<_florent_> tnt: The BIOS is detecting presence of peripherals from presence CSR names , so for now I would recommend renaming your submodules
<tnt> ack
<mntmn> if i have some IP that has an interrupt line which is "level triggered", do i have to do some special stuff to make it work correctly with vexriscv interrupt lines?
<mntmn> i suspect that the cpu is triggering on edges only?
<mntmn> to explain better, i can see in /proc/interrupts that the interrupt was recognized many times but it has stopped counting now:
<mntmn> 4: 2673 SiFive PLIC 16 Edge ue11-hcd:usb1
<mntmn> but in litescope i can see that the interrupt line is high
<mntmn> _florent_: any idea? does an interrupt line from hdl to vexriscv have to be pulsed?
<_florent_> The cores from LiteX generate level triggered IRQs and that's what I also think is expecting VexRiscv-SMP PLIC implementation
<_florent_> So your integration should be similar to IRQs generated from the UART/LiteEth cores
<mntmn> hmm, but what could cause interrupts to not be registered?
<mntmn> i.e. i can see in litescope the line is high, but counter in /proc/interrupts does not increase
<_florent_> I also don't explain it, unless we have a current missmatch between LiteX IRQs and expexted VexRiscv-SMP IRQs
<_florent_> can you try to modulate the IRQ from your core, just to see if you then see the interrupt increasing?:
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<mntmn> _florent_: ok, i'm gonna try that
<mntmn> thanks!
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<jersey99> _florent_ Sorry for the bother, but I kind of want to see this through :) .. but are there any unassumed constraints about the BOOT_ROM_ADDRESS? The region seems to get allocated fine during build (base at 0x2000_0000), and I see the CPU trying to jump to that region after bios.
<jersey99> And unexpectedly, setting the edianness to correct "little" didn't change the behavior
<_florent_> before compiling the litex_bare_metal_demo, are you also updating:
<_florent_> to use the new memory you added?
<mntmn> hmm, what would make litescope not continue anymore after [running]...? (with immediate capture). i think i broke it by adding a 12-bit signal to the capture list
<mntmn> ah, the problem was outdated csr.csv
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<jersey99> Oh .. Do I need to explicitly add the extra regions to the CPU? In that case, to my eyes, I don't see csr region being explicitly added. I will look into this
<tcal> tnt: my iceprog doesn't seem to have "-Q" ?
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<jersey99> _florent_ .. Thanks a lot for your help. This makes a lot of sense, and works :)
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<jersey99> _florent_ I made a minor edit here ( https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU ) in regards to my experience. Maybe you could say something about the linker script (I understand it's a side detail).
<tnt> tcal: oh, my bad, this PR never got merged ... https://github.com/YosysHQ/icestorm/pull/283
<bjonnh> those digilent boards are shipping from Taiwan!
<tcal> tnt: thanks for the pointer, hopefully I can check tonight if it unjams the board
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