_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> nickoe: The issue seems related to write latency calibration, you can try to disable it by commenting: https://github.com/enjoy-digital/litedram/blob/master/litedram/init.py#L921-L922
<nickoe> _florent_: Hmm, ok I am not sure if there was a way to change it, but I just modified the default set in class S7DDRPHY(Module, AutoCSR): and rebuilt it, now it do seems to pass with OK. https://dpaste.com/64WCPW3DL.txt
<nickoe> Is that a "new feature" or is that a clear indication on something I may have misconfigured?
<nickoe> I set the settings to what is described in https://download.enclustra.com/public_files/FPGA_Modules/Mars_AX3/Mars_AX3_User_Manual_V06.pdf page 25 or section 2.14.4 Parameters
<nickoe> Now ehn I try to load the demo.bin it does not appear to run.
<nickoe> but I note this when I build it: warning: memory region `main_ram' not declared full log: https://dpaste.com/CP7JNT8PU.txt
<nickoe> I should be on the latest commit of litex so this "should" be included https://github.com/enjoy-digital/litex/pull/1007
<nickoe> But something must have changed, because the old demo.bin on an sdcard fails the same way. Maybe there are more that I ened to change to run agianst the latest litex.
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<nickoe> Is there a good way to install the symbiflow toolchain for use with litex+
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<_florent_> nickoe: The default main_ram has been removed from the simulation, you have to explicitly enable it (with --integrated-main-ram-size or --with-sdram)
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<nickoe> Mm, ok, _florent_, but does it explain why it does not run on hardware?
<nickoe> I do like this when building ./mars_ax3.py --build --integrated-rom-size=0x10000 --with-spi-sdcard --load --csr-csv=csr.csv
<nickoe> When I add --integrated-main-ram-size 0x10000 I get: AttributeError: 'BaseSoC' object has no attribute 'sdram'. Did you mean: 'sram'?
<nickoe> i guess I should double check I can run the demo app in lxsim..
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<nickoe> How is it that I load the demo.bin in the simultor lxsim? It is not mentioned here, only with lxterm, https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU
<nickoe> iI can make the lx_server connecto the sim and use litex_cli to get the ident from the simulation, BUT how do l load the demo.bin then?
<tpb> Title: #litex on 2021-04-20 — irc logs at whitequark.org (at freenode.irclog.whitequark.org)
<nickoe> _florent_: But it does not run for me, I just get the Liftoff!
<nickoe> that is "litex_sim --ram-init=demo.bin"
<nickoe> Just running litex_sim boots the bios just fine.
<_florent_> litex_sim --integrated-main-ram-size=0x10000
<nickoe> I am on litex commit 321b91d5 (HEAD -> master, origin/master, origin/HEAD) Merge pull request #1134 from fjullien/efinix_titanium_support
<_florent_> litex_bare_metal_demo --build-path=build/sim
<_florent_> litex_sim --integrated-main-ram-size=0x10000 --ram-init=demo.bin
<nickoe> The last one do run
<nickoe> So maybe I need to migrate from --integrated-rom-size=0x10000 to --integrated-main-ram-size=0x10000 in my target?
<nickoe> _florent_: Is that --ram-init option supposed to support a boot.json?
<nickoe> For me it appaers that Vsim (verilator) crahes
<nickoe> %Error: mem_2.init:16384: $readmem file address beyond bounds of array
<nickoe> Mm, I can't figure out why i errors with thatit not being able to find the sdram attribute ... maybe I should take a walk and get some fresh air
<nickoe> self.sdram.crossbar.get_port(mode="read", data_width=32, reverse=True),
<nickoe> Has this construct changed? I mean, the location of the sdram object?
<_florent_> except adding the --integrated-main-ram-size, things haven't changed
<nickoe> This is my code, and as far as I can tell it does not like the self.sdram anymore there
<nickoe> maybe caused my be not doing theese changes properly?? https://github.com/nickoe/litex-boards/commit/5eecf4f5b49a25bc386e15ed6120863e5efb6f6c
<nickoe> I can't explain why the self.sdram does not exist, but I can't really explain how it get added in the first place because of the attr magic chcecks, so it is a bit hard to navigate.
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<nickoe> When I don't add the new --integrated-main-ram-size then it builds fine.. so it must be dependent on that.
<nickoe> well, there is of couser tthe check here.. https://github.com/nickoe/litex-boards/blame/mars_ax3_sim_2021.12.18/litex_boards/targets/mars_ax3.py#L129-L144 but should I just remove that check?
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<nickoe> hmm, no it appears that sections is called a couple of time.
<nickoe> When "if not self.integrated_main_ram_size and with_sdram:" is not true, hos is the add_sdram then called for the litex_sim.py?
<nickoe> I can't figure out how to add a brakpoint on just a function name in pycharm.
<nickoe> oh, right, I could of course just break in the function
<nickoe> So it is not called.. _florent_ how is self.sdram then added in the case of "litex_sim --integrated-main-ram-size=0x10000 --ram-init=demo.bin --with-sdram"
<nickoe> mm, maybe I don't want integrated-main-ram-size at all for my setup?
<nickoe> Is that some sdram that is insude the fpga for some models or?
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<mikek_DE1SOC> Florent: tnt: Great news !! I wa able to compile the fairwaves.py script!! Let me know what you wanted for me to do next!!!
<tpb> Title: Fairwaves_compile - Pastebin.com (at pastebin.com)
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<mikek_DE1SOC> But just to clarify! I have the OLD XTRX, the first generation first generation of the card. Not sure if the FPGA is xc7a__50__tcpg236-2??? I think mine is the 35.
<mikek_DE1SOC> unless they only made 1 version...
<mikek_DE1SOC> yeah the CS is the 35....