<nickoe>
_florent_: Hmm, ok I am not sure if there was a way to change it, but I just modified the default set in class S7DDRPHY(Module, AutoCSR): and rebuilt it, now it do seems to pass with OK. https://dpaste.com/64WCPW3DL.txt
<nickoe>
Is that a "new feature" or is that a clear indication on something I may have misconfigured?
<nickoe>
But something must have changed, because the old demo.bin on an sdcard fails the same way. Maybe there are more that I ened to change to run agianst the latest litex.
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<nickoe>
Is there a good way to install the symbiflow toolchain for use with litex+
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<_florent_>
nickoe: The default main_ram has been removed from the simulation, you have to explicitly enable it (with --integrated-main-ram-size or --with-sdram)
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<nickoe>
Mm, ok, _florent_, but does it explain why it does not run on hardware?
<nickoe>
I do like this when building ./mars_ax3.py --build --integrated-rom-size=0x10000 --with-spi-sdcard --load --csr-csv=csr.csv
<nickoe>
When I add --integrated-main-ram-size 0x10000 I get: AttributeError: 'BaseSoC' object has no attribute 'sdram'. Did you mean: 'sram'?
<nickoe>
i guess I should double check I can run the demo app in lxsim..
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<nickoe>
So maybe I need to migrate from --integrated-rom-size=0x10000 to --integrated-main-ram-size=0x10000 in my target?
<nickoe>
_florent_: Is that --ram-init option supposed to support a boot.json?
<nickoe>
For me it appaers that Vsim (verilator) crahes
<nickoe>
%Error: mem_2.init:16384: $readmem file address beyond bounds of array
<nickoe>
Mm, I can't figure out why i errors with thatit not being able to find the sdram attribute ... maybe I should take a walk and get some fresh air
<nickoe>
I can't explain why the self.sdram does not exist, but I can't really explain how it get added in the first place because of the attr magic chcecks, so it is a bit hard to navigate.
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<nickoe>
When I don't add the new --integrated-main-ram-size then it builds fine.. so it must be dependent on that.
<nickoe>
hmm, no it appears that sections is called a couple of time.
<nickoe>
When "if not self.integrated_main_ram_size and with_sdram:" is not true, hos is the add_sdram then called for the litex_sim.py?
<nickoe>
I can't figure out how to add a brakpoint on just a function name in pycharm.
<nickoe>
oh, right, I could of course just break in the function
<nickoe>
So it is not called.. _florent_ how is self.sdram then added in the case of "litex_sim --integrated-main-ram-size=0x10000 --ram-init=demo.bin --with-sdram"
<nickoe>
mm, maybe I don't want integrated-main-ram-size at all for my setup?
<nickoe>
Is that some sdram that is insude the fpga for some models or?
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<mikek_DE1SOC>
Florent: tnt: Great news !! I wa able to compile the fairwaves.py script!! Let me know what you wanted for me to do next!!!
<mikek_DE1SOC>
But just to clarify! I have the OLD XTRX, the first generation first generation of the card. Not sure if the FPGA is xc7a__50__tcpg236-2??? I think mine is the 35.