15:50 <keesj> Hi. it has been a long time but I am back a litex. I would like to integrate and possibly first debug verilog wishbone slave into my design.

15:51 <keesj> later I also want to use boneuart and perhaps also add some autocsr fields it this can be combined

15:55 <keesj> I have done some digging and trying and I wonder .. can I create a Interface with the correct fields and pass it to soc.bus.add_slave?

15:58 <keesj> https://gist.github.com/keesj/7562d07053a70320b7e1ca663e1d0b65 (something like that?)

16:08 <keesj> my target is a colorlight i9 (ecp5)

16:22 <keesj> https://github.com/enjoy-digital/litex/wiki/LiteX-for-Hardware-Engineers/8d163ba301a66fa2627b5eb1332936dd2635a8f3#wishbone-rw-logic-ro is also trying to tell me something