_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sajattack> when I increase this variable (to 16MB bar size) it just breaks litepcie_util info and dmesg also reports ffffffffffffffffffffffffffffff for the device name or whatever. The bar size reported by sysfs remains 1MB, and the device is unusable. For a while I thought something was wrong with my programming procedure but it turns out that once I lower it back to 1MB everything's happy
<tpb> Title: b2fe93a — paste.sr.ht (at paste.sr.ht)
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<sajattack> sorry if it seems like I'm complaining a lot, just trying to get back up to speed and hitting a few roadblocks
<sajattack> yes, yes it is
<sajattack> how do I define what the bar maps to?
<tnt> It connects to the global "SoC" address space basically.
<sajattack> at what address offset?
<tnt> I use something like self.bus.add_slave(name="radio", slave=mybus, region=SoCRegion(origin=0xf0040000, size=0x40000, cached=False)) to connect a custom wishbone peripheral to part of it.
<tnt> I think it starts at 0xf0000000
<sajattack> thanks
<sajattack> my goal right now is to display a single colour other than black or white on my framebuffer. time to figure out wishbone
<sajattack> thankfully found this https://github.com/enjoy-digital/litex/issues/1368