_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
TMM_ has quit [*.net *.split]
jeffdi has quit [*.net *.split]
ilia__s has quit [*.net *.split]
joseng has quit [*.net *.split]
jeffdi_ is now known as jeffdi
tpb has joined #litex
jeffdi1 has joined #litex
TMM_ has joined #litex
joseng has joined #litex
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
futarisIRCcloud has joined #litex
<bjonnh> guess what, just received an update from ulx3s…
<bjonnh> so I'll have two boards
Degi_ has joined #litex
Degi has quit [Ping timeout: 256 seconds]
Degi_ is now known as Degi
peepsalot has quit [Quit: Connection reset by peep]
peepsalot has joined #litex
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
<trabucayre> I suppose If I order something in digilent shop I will have VAT & customs fees to EU shipping ?
Martoni42 has joined #litex
<tcal> Hmm, I can't get the litex-boards build for iCEBreaker (non-bitsy) to work. The LEDchaser is working, but I can't connect to BIOS over the tty. I feel like I'm forgetting something. `./1bitsquared_icebreakder.py --cpu-variant=minimal --build --flash`. I've tried vex:lite, vex:minimal, and serv. I did try pushing the uButton, which does seem to reset it (looking at the LEDchaser), but still nothing over the tty.
<tcal> (ignore the typo above, I retyped it here - the typo wasn't in the original command)
<tnt> Are you sure the issue doesn't lie with the way you connect to the tty ?
<tcal> Well, I'm trying `lxterm --speed 115200`, but then realized I didn't know how to determine the baud rate from the build artifacts.
<tnt> and are you using ttyUSB1 ?
<tcal> Yep, that's what I see appear under /dev
<tcal> So yes, `lxterm --speed 115200 /dev/ttyUSB1` is the full command
<tnt> tbh I never used lxterm so no clue if that's correct. I just use minicom.
FabM has joined #litex
FabM has quit [Changing host]
FabM has joined #litex
<tnt> Mmm ... doesn't seem to work for me either FWIW
<tnt> Oh nm, it works fine. pebkac
Martoni42 has quit [Ping timeout: 252 seconds]
<tcal> Hmm, thanks for checking! Which CPU / variant did you use? And you met timing?
<tnt> i used your exact line from above.
<tnt> And no, it didn't meet timing.
<tnt> Warning: Max frequency for clock 'main_crg_clkout': 22.17 MHz (FAIL at 24.00 MHz)
<tcal> Thanks, yeah, I was missing with 23.xx, and then SERV met timing, but the SoC still didn't work for me. I'll try again tomorrow I think :)
jeffdi1 has quit [Quit: Leaving.]
essele_ has quit [Read error: Connection reset by peer]
essele has joined #litex
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
zjason` is now known as zjason
jeffdi1 has joined #litex
<essele> Can anyone give me a clue how to add io pins to a project. I'm using a ulx3s and want to make use of pin B17. If I use "add_extension([("name", 0, Pins("B17"))])" then I get an "TypeError: 'NoneType' object is not iterable" error when requesting it. It works fine if I edit the litex-boards/platform file and add it in, but I'm trying to avoid that.
<acathla> essele, instead of specifying directly the pin, you must use the connector_number:pin_number
<acathla> I did it like that: serial = [ ("serial", 0, Subsignal("tx", Pins("J3:0")), ... )] Where J3 is the connector name and 0 pin number.
<acathla> And then I can do an add_extension(serial)
<essele> Thanks @acathia .. but it's not on a connector, the pin is one of the expansion pins on the ulx3s (B17) which isn't mentioned at all in the platform file. Does that mean it's not possible? The only approach is to completely populate the platform file with all of the pins?
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
<mntmn> hey so... i managed to integrate ultraembedded core_usb_host and core_ulpi_wrapper in litex, and the linux driver for it works as well. i just need to wire up 1 IRQ line somehow
<mntmn> in the target python, i have a usb_host_intr = Signal()
<mntmn> how do i wire this up to the interrupt-controller?
<mntmn> (sifive,fu540-c000-plic)
FabM has quit [Ping timeout: 268 seconds]
<mntmn> should i use add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False)?
<mntmn> ah, if i have this: self.comb += self.cpu.interrupt[16].eq(usb_host_intr)
<mntmn> that's interrupts = <16>; in the dts, yeah?
<jersey99> _florent_ Any wisdom on the boot/serialboot?
Martoni42 has joined #litex
<_florent_> jersey99: is the demo.bin the binary generated with litex_bare_metal_demo? Have you adapted the address (it seems you use 0x2000_0000, the demo probably uses 0x4000_0000 (main_ram)?
<_florent_> Also it seem you are using endianness="big", RISC-V CPU are "little"
<jersey99> Oh .. Let me look at that!
<jersey99> very likely the big/little
<jersey99> I think the addresses are fine. Unless there is a hard coded address inside the demo itself
<jersey99> _florent_ Thanks for getting back, this should help!
Degi has quit [Ping timeout: 252 seconds]
Degi has joined #litex
zjason` has joined #litex
zjason has quit [Ping timeout: 256 seconds]
Martoni42 has quit [Ping timeout: 268 seconds]
<jersey99> _florent_ I am wondering if this has something to do with address disparity between SerialBoot and RomBoot. I see that lxterm uses 0x4000_0000 as boot_address for serialboot. In my test code with kc705, I build the demo.bin with demo.py, and set the BOOT_ADDRESS explicitly in BaseSoC to 0x2000_0000, after loading that memory with demo.bin. Am I
<jersey99> missing something?
<jersey99> I think I may have a lead after looking at boot.c
<jersey99> Actually, I don't. Looks like ROM_BOOT_ADDRESS is all I have. For a second I got confused with FLASH_BOOT_ADDRESS
<mithro> People here might find https://twitter.com/proppy/status/1466020384063430657?s=20 interesting