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<shoragan> somlo, with the updated pythondata-cpu-rocket, it now builds a bitstream using the hdl containers and current lites_setup: https://github.com/jluebbe/linux-on-litex-rocket/actions/runs/870508716
<shoragan> it still fails to print anything from the bios for me though, on the ECPIX-5.
<shoragan> it reports "Warning: Max frequency for clock '$glbnet$sdrio_clk': 21.52 MHz (FAIL at 50.00 MHz)"
_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
<somlo> shoragan: with latest rocket, litex, and toolchain I get bitstream that fails dram initialization (memtest KO); I got that as soon as I updated rocket (with the old toolchain), but with the new toolchain I can't downgrade rocket without getting another error (something about "resetctrl_hartIsInReset_0")
<somlo> at this point I'm still running some tests before deciding where to start asking for help :)
<zyp> _florent_, do you have a moment to have a look at litex#915 and litespi#47?
<shoragan> the "resetctrl_hartIsInReset_0" error is exactly what i had before the rocket upgrade
<shoragan> i also tested with ubuntu 20.04 (instead of 18.04), but that doesn't make a difference
<shoragan> somlo, hmm. building for vexriscv-smp i also get the 'Memtest KO', but at least the bios starts
<geertu> _florent_: Am I misremembering that linux-on-litex-vexriscv "make.py --load" did update the BIOS ROM in the bistream?
<geertu> These days it rebuilds the BIOS, but doesn't update the ROM data in the bitstream, so you still end up using the old version, which is annoying if you made modifications.
<shoragan> somlo, to check that my issue is not a miscompiled bios, i used litex_sim with --cpu-type rocket. that starts into a working bios
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<_florent_> zyp: sorry, I'll look at them tomorrow
<zyp> thanks :)
<_florent_> geertu: ./make.py --load in Linux-On-LiteX-Vexriscv never updated the ROM in the bitstream :)
<_florent_> this could be an interesting feature, but would have to be handled differently for each FPGA family
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<zyp> it'd also be useful to combine with dependency tracking for the whole build pipeline so that it'd automatically decided whether it needed to rebuild the gateware or not
<zyp> I was playing around with that a little bit last year, but I didn't take it far enough to get anything usable
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