_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> tcal: yes exactly, doing the CFU instance in the do_finalize will allow you to update self.cfu_params from your user design, method calls, etc...
<_florent_> tnt: You can indeed simplify the clocking, this design supports 2 JESD linerates (transceivers reconfigured over DRP), I removed the DRP part before sharing but forgot to simplify the clocking.
<tnt> _florent_: thanks for confirming. Now I gotta make it work on USP, looks like it doesn't accept the GTH3 primitives, gotta make them GTH4.
<_florent_> tnt: Indeed, if seems LiteICLink currently only supports GTHE3/Ultrascale and GTYE4/UItrascale+
<tnt> Yup that's unfortunate because looking at those files, it seems insanely complex.
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<tnt> _florent_: you don't happen to have the xci file that was used to get the original transceiver config ?
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<tcal> _florent_: yep, that works for me! PR incoming.
<_florent_> tnt: I should have it and will try to find it. I think GTHE3/GTHE4 are very similar, to get a first idea about this, could you generate the default transceiver wizard configuration for both and compare the generated files? (and GTHEX instances?)
<tnt> They definitely look very similar and even explained in the same document with the same tables with just some notes about "Ultrascale only" / "Ultrascale+ only" but there are a bunch of "reserved values" in those differences.
<tnt> _florent_: I generated both in default config. Unfortunately some of the magic values are different :/
<tnt> I'll make a table comparing both along with the "default" values of the params you find in the sim model.
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<_florent_> tnt: OK, I'll also have a look
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<tpb> Title: GTHE3/4 compare (at people.osmocom.org)
<tnt> first draft
<tnt> (just for COMMON atm)
<tpb> Title: GTHE3/4 compare (at people.osmocom.org)
<tnt> Now "just" need to analyze them and figure out what's needed.
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<tnt> There are a bunch of params that have a _G3 suffix, any clue what that means ?
<_florent_> tnt: thanks, sorry I'm not able to help much now (busy on something else), but maybe you could start adapting the instance (remove the parameters that are specific to GTHE3, add the ones that are specific to GTHE4), same for signals and we could then have closer look together at the differences/parameters. This should also allow you to test design compilation.
<tnt> _florent_: yeah, working on that right now. This is what it looks like ATM: https://pastebin.com/WQtN3jR5
<tpb> Title: diff --git a/liteiclink/serdes/gth_ultrascale.py b/liteiclink/serdes/gth_ultrasc - Pastebin.com (at pastebin.com)
<tnt> (completely untested ... obviously )
<_florent_> tnt: Looks good. Before testing JESD with this wrapper, we'll probably be able to do a first simple test with liteiclink examples
<_florent_> tnt: with the internal loopback, at various rates and eventually with others boards if you (or I) have boards with some GTHE4 transceivers exposed to some connectors
<_florent_> tnt: This way the link will validated before being integrated for JESD
<tnt> _florent_: Ack. Probably a good idea indeed :)
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<paul-web> Has there been any thought for including ARM Cortex-M processors with the understanding the user would be responsible to provide the SDK.
<paul-web> It's freely available (as in beer) via Arm DesignStart (both M1 and M3). From my brief look it doesn't seem like a giant leap to support given the framework already in place
<paul-web> or am I just way underestimating the amount of work required?
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<bjonnh> oh my… the UART in connected to the PS and not the PL
<bjonnh> that's not going to be fun
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<tnt> bjonnh: lol, had the same thing recently ... ended up putting a usb->serial on some random gpio because you can't connect MIO pins to the PL.
<bjonnh> of course I don't have that
<bjonnh> I was thinking about flashing the PS with something that would do that
<bjonnh> which mean that I have to learn how that PS work
<tnt> yeah, you could use one PS uart connected to MIO, another one connected to the PL and then have a software running shuffling chars arounds. That would work I guess. Painful, but that would work.
<tnt> What board is it btw ?
<bjonnh> Arty Z7-20
<bjonnh> but I don't understand it seems that to use the PS I need to have some stuff ready in the PL
<bjonnh> which mean that I may not be able to do that with symbiflow, yosys etc
<bjonnh> tbh I don't know how most of that work just yet
<tnt> Mmm .. no the PS can work independently from the PL.
<tnt> Specifically to support systems where the PS is the one loading the PL.
<bjonnh> ok I have to investigate that further then
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