02:34 <yootis> _florent_: What's the status of running litescope over PCIe with the kernel module installed and the interface active?

04:52 <taylor-bsg> Hi, we have been looking at broader Ethernet and interrupt support for BlackParrot Linux systems. Leveraging the Litex ecosystem in yet another way, we have developed an SystemVerilog LiteEth compatible MAC, that is compatible with the Linux driver. However, we are trying to puzzle through the interrupt situation. It looks like the upstreamed

04:52 <taylor-bsg> LitEth driver leverages interrupts in the Linux LiteEth driver? For Rocket Litex, it presumably uses the PLIC, but it wasn't clear to me what happens for VexRisc Litex. Is there an intent longer term for Litex to have a interrupt device in Linux, or is Litex intending to implement PLIC, or ... ?  One thing we have been looking at is extending

04:52 <taylor-bsg> LiteEth so that it can use per-CPU interrupts. In any case looking forward to any thoughts or insights on the IRC!

08:44 <_florent_> yootis: I'll need to have a look at this, for now you can eventually use another bridge for LiteScope (ex JTAGBone)

08:57 <_florent_> taylor-bsg: For now we are relying on PLIC for both Rocket/VexRiscv (implemented in the CPU). We are doing things progressively and could eventually have/move the interrupt controller directly in LiteX in the future.

11:54 <nickoe> Hello. Why does the litex_setup.py script complain like this?? https://dpaste.com/GMTT275NW.txt

11:55 <nickoe> oh, itis the litex repo it complains about not the other one

11:56 <nickoe> mm, not it happened in another repo as well

11:56 <nickoe> Why does that happen? https://dpaste.com/674KZHGKD

11:56 <tpb> Title: dpaste: 674KZHGKD (at dpaste.com)

12:00 <nickoe> It succeded now after a couple of stashes...

12:18 <Wolf0> _florent_: I have some details about the FK33 your thing is missing!

12:18 <Wolf0> Also, do you do voltage control at all? Cause I have *just* the thing...

12:23 <Wolf0> I describe the available flash here: http://lovehindpa.ws/writings/fk33-detail.php

12:23 <tpb> Title: Wolf9466's GPU & FPGA Writings (at lovehindpa.ws)

12:23 <Wolf0> of note - for ultra-fast confguration, consider using dual-quad mode! :3

12:24 <Wolf0> There's two MT25QU256 chips wired up for that configuration if you want it.

12:31 <nickoe> Anyone using PyCharm for litex stuff?

14:05 <nickoe> I see litevideo was removed in https://github.com/enjoy-digital/litex/commit/9b4c7e8288c468eb84acdb8285a9e8a9f30677bc I have been using DMAReader from that, is there a direct alternative now?

14:05 <nickoe> LiteDRAMDMAReader ?

14:36 <_florent_> Wolf0: The HBM2 support on the FK33 was just a quick test, if you know things that can be improved feel free to share, we could integrate this.

14:37 <_florent_> nickoe: I indeed no longer maintain/recommend LiteVideo (too old, difficult to maintaint), for video output you can now use the video core from LiteX that is indeed probably using the LiteDRAMDMAReader.

14:48 <nickoe> ok, I am just trying to pick up my older unfinished project

14:49 <Wolf0> _florent_: no, I mean, on the page, it says "Flash: Unknown"

16:18 <nickoe> Mmme, somone who can remmint me how to use boot.json with the sim

19:52 <nickoe> How do I use a boot.json for the simulator in the latest litex? IIRC there was a specific arg that took a boot.json

19:52 <nickoe> mm, possibnly --rom-init or --ram-innit

20:20 <mithro> _florent_: Do you know what MicroWatt / mor1kx is using for interrupt stuff under Linux?

20:28 <nickoe> Mm, in verilog is it not allowed to define a signal like "output wire o_tvalid" of the module as change it like: "o_tvalid <= 1; " ? Trying ot build something with a verilog provided by a friend.

20:28 <nickoe> ..

20:28 <nickoe> but vivado complains

20:28 <nickoe> ERROR: [Synth 8-2576] procedural assignment to a non-register o_tvalid is not permitted

20:50 <leons> You can only ever have one simultaneous (i.e. combinational) assignment for a signal, for procedural assignments use a reg. Arguably I think the differentiation between those types is a little weird when you come from Migen.

20:55 <nickoe> Hmm, yeah, that sorta makes sense to me. I is quite a while since I played aroundw ith this so my verilog is quite rusty, and I has always been a newbie anyways.

20:56 <nickoe> I did some mods here and there and not now synthesized completely

21:20 <nickoe> mm, ok, finally something booted, but ram test fails ..

21:21 <nickoe> It did work well last time I had it, maybe I am missing some adjustments to the ram params somwhere in the void

21:24 <nickoe> https://github.com/nickoe/litex-boards/blob/1efa41b589b889cae3f895368fd733d84e774f38/litex_boards/targets/mars_ax3.py#L88-L108

21:25 <nickoe> I am not sure how to interpret the output of the sdram test "graphs" https://dpaste.com/5STZF8MQE

21:25 <tpb> Title: dpaste: 5STZF8MQE (at dpaste.com)

21:40 <nickoe> The tRFC tuples, what does the numbers mean there? tRFC=(None, 350),

21:40 <nickoe> it appoaers that the datasheet says "tRFC(ns)5160ns"

21:41 <nickoe> the 5 being a footnote

22:12 <nickoe> How can I verify that it is using the correct row in the timing settings that I expect?

22:17 <nickoe> AS a sanitty check

23:04 <nickoe> _florent_: Has something changed in litedram that I should be aware of that could cause these issues?