_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<mikek_DE1SOC> Hi Florent: I am getting a new error when trying to compile a Linux-on-litex-vesrisc..
<mikek_DE1SOC> Traceback (most recent call last):
<mikek_DE1SOC> File "./make.py", line 746, in <module>
<mikek_DE1SOC> soc.generate_dts(board_name)
<mikek_DE1SOC> main()
<mikek_DE1SOC> File "./make.py", line 727, in main
<mikek_DE1SOC> File "/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Nov2021/linux-on-litex-vexriscv/soc_linux.py", line 164, in generate_dts
<mikek_DE1SOC> dts_content = generate_dts(json.load(json_file), polling=False)
<mikek_DE1SOC> File "/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Nov2021/litex/litex/tools/litex_json2dts_linux.py", line 68, in generate_dts
<mikek_DE1SOC> linux_initrd_start = d["memories"]["main_ram"]["base"] + initrd_start,
<mikek_DE1SOC> KeyError: 'main_ram'
<mikek_DE1SOC> (Litex_Nov2021) mikek@mike-AERO-17:~/Documents/Cyclone5_SOC/Litex_New_release_Nov2021/linux-on-litex-vexriscv$
<mikek_DE1SOC> I did a litex-setup --update..
<mikek_DE1SOC> FYI I have also got to work in litex-boards (De1Soc) already there, the Deca Board and the DE10-Nano with my Sram that I got..
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<mikek_DE1SOC> Good news is that Litex-boards build and loads fine.
<mikek_DE1SOC> Sorry that this seems so simple..
<mikek_DE1SOC> I am new and still learning... :)
<mikek_DE1SOC> DOH I am sorry!!!
<mikek_DE1SOC> I got it....
<mikek_DE1SOC> I was playing in the litex boards file and delected out my RAm....
<mikek_DE1SOC> DOH!!!!!
<mikek_DE1SOC> Solved...
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<jevinskie[m]> Luckily you can just download more RAM with `git checkout` ;)
<sajattack[m]> Assuming github is online