_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<jersey99> _florent_ I am having some trouble where the Litex BIOS doesn't boot when the CPU is built with uart=crossover. It only boots when I have the litex_server running. Is there some interrupt the CPU is waiting for in order to boot?
<jersey99> Note the CPU boots normally when the uart isn't being used in crossover mode
<jersey99> *the CPU only boots when I have the litex_server running AND run "litex_term crossver"
<_florent_> jersey99: With the crossover UART, the UART is indeed handling backpressure from the destination, which stalls the CPU when destination is not ready/enabled.
<_florent_> jersey99: I added this to still allow the CPU to boot in this case:
<jersey99> Aha!
<_florent_> This adds some logic to detect this situation and flush the data
<jersey99> let me take a look. Thanks a lot!
<jersey99> That is fair
<_florent_> But you need to enable it manually since this is not necessarily wanted in all situations
<jersey99> Yes, totally makes sense!
<jersey99> That's a really cool project :)
<jersey99> Have you managed to come up with a LiteLVDS? :) .. So far I have interfaced 1 LVDS adc with migen/Litex and it's not clear to me if there will ever be benefit in making something generic with this
<jersey99> _florent_
<_florent_> The ADC/DAC protocols are often a bit specific, if we see this could be useful to have a common core for this in the future we could think of it
<_florent_> paul-web: We are currently playing with hard Cortex-M on QuickFeather/TangNano4K to improve ARM support in LiteX, it would also be interesting to try the ARM softcores too and should be very similar. But we would also need to study the licenses a bit to see what can be shared...
<jersey99> sounds good
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<paultech> _florent_: Good to know regarding ARM and QuickFeather/TangNano4K.
<paultech> I figured licensing would be a sticky issue - Brief review (the licensing document is surprisingly short for something like IP) seems to show if user provides the *.vp/tcl files there would be no violation.
<paultech> The documentation needed to host the CPU is openly available - https://developer.arm.com/documentation/ddi0413/d
<paultech> You may even find ARM has a positive attitude to the litex inclusion, They've stated the Cortex FPGA line M1/M3 goal in life is to be a rapid proof of concept prototyping core. Cant be better than LiteX for that ;)
<tpb> Title: Documentation – Arm Developer (at developer.arm.com)
<tnt> At least it builds without fatal error. No clue if it works though.
<Wolf0> _florent_: are you interested in expanding FK33 support? I could maybe help with some things.
<paultech> How are the LiteSPI modules generated? The Arty S7 uses a S25FL128S (S25FL128SAGMFx00 according to datasheet). The datasheet shows it supports quad read but the generated module only has READ_1_1_1
<_florent_> tnt: thanks, in fact I'm sorry but I'm realizing that duplicating the code between GTHE3/GTHE4 (even if most parameters are common) could still be interesting, since it allows easy comparison with the wrapper generated by the wizard and use useful for configuration that haven't yet been yet, so I'll have to think about the best way to merge this.
<_florent_> Wolf0: yes, it would be useful to have an example design the the FK33 with SoC + PCIe + HBM
<paultech> Ah seems to come from the flashrom project files - https://github.com/flashrom/flashrom/blob/master/flashchips.c#L16174
<_florent_> Wolf0: I wanted to create a project to create FPGA accelerators with LiteX (and cores), using the Acorn, XCU1525 and FK33 as first supported boards, but haven't spent too much time on it yet
<_florent_> Wolf0: If that's something you are interested and want to help on that, we could improve the FK33 support there (LiteX-Boards is a bit too generic for this)
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<_florent_> paultech: I also noticed this some time ago: https://github.com/litex-hub/litespi/issues/55
<_florent_> the generation should be improved
<paultech> Still confirming my issue but I believe what I actually wanted was 'S25FL128S0' which maps to flashroms '.name= "S25FL128S......0",' module which does seem to match the datasheet and partnumber in use.
<paultech> The CLK for SPI is incorrect in the Arty S7 platform, testing it now
<paultech> Useful information in there, thanks
<_florent_> paultech: Sorry, not sure to understand the issue
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<tnt> _florent_: heh before merging it, it'd be good to check it works :)
<_florent_> tnt: yes sure, but before you spend too much time, I was just sharing my thought on this :)
<_florent_> when I need to support a new protocol, what I do generally is that I generate the wrapper with the wizard and then do a comparison of liteclink wrapper/Xilinx wrappers (the parameters are in the same order)
<_florent_> so while merging things can seem a good idea, it could also prevent this, so has advantages/disadvantages
<_florent_> I need to check if I the Ultrascale+ boards I have have GTHE4 transceivers, if so I could do a LiteICLink test
<tnt> I see. I wrote a python script that parses the wrapper generated code and unisim model to extract default values and used values and "sort them". (to find gthe3 / gthe4 differences and what's non-default, etc ...)
<tnt> Unfortunately the board I have doesn't have anything exposed on SMA :/
<tnt> I guess maybe a SFP+ transceiver and a fiber loopback would do the trick.
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<paultech> https://github.com/litex-hub/litex-boards/blob/9119250276b9fd7e0a738eebf31b3e84a3a479b5/litex_boards... -> Incorrect spiflash4x.clk (don't believe you need to route a clk here?)
<paultech> https://github.com/litex-hub/litex-boards/blob/9119250276b9fd7e0a738eebf31b3e84a3a479b5/litex_boards/targets/digilent_arty_s7.py#L80 -> Uses Python module 'S25FL128S' which does not support Quad Read. The desired Python module that matches the part number is S25FL128S0 (note the trailing 0)
<paultech> I'm currently exploring litex so I may be way off but that and setting CONFIG_VOLTAGE in accordance with the XDC for the Arty S7 seems to give me working quad flash on the board
<paultech> Arty S7 does build and boot with those changes (sorry, webclient for irc is not ideal and is dropping messages. I'll jump on a proper client here shortly)
<_florent_> tnt: SFP+ transceiver + fiber loopback will work yes, I'm generally using a SFP loopback module for these tests
<_florent_> tnt: I just try to stay with copper initially since no need to handle tx_disable (with is sometimes inverted on some boards)
<_florent_> tnt: as an initial test, you can also just use the internal loopback, in the PCS, then in the PMA and once both are OK, test with the external loopback
<tnt> Yeah, I'll see if they have anything that can do loopback ... (still don't have a board locally ... ordered but it's taking forever)
<_florent_> For the test, you can use the test_prbs script here: https://github.com/enjoy-digital/liteiclink/blob/master/bench/serdes/test_prbs.py
<_florent_> (just need a UARTBone bridge to the SoC)
<_florent_> you can enable internal loopback with --loopback
<tnt> Ack, I'll dig into that and see if I can get that running.
<tnt> BTW, unrelated, but how do you suggest to handle the patch I need to litepcie to change the Quad location ? Currently I just patch my local install .xci but ideally I'd like to have a "basic" version of the ADRV2CRR-FMC platform/target put into litex-boards but obviously it would need that patched version to build.
<_florent_> tnt: we should probably do something similar to what ilia__s just did for 7-series: https://github.com/enjoy-digital/litepcie/commit/6ef3cba6ad077cda1f68090576377333d58d07bc
<_florent_> tnt: this will allow you to just generate the PHY from the tcl script/parameters
<_florent_> tnt: but before this, we have to do https://github.com/enjoy-digital/litepcie/issues/42 (or at least move the verilog code that has been integrated in the PHYs)
<tnt> Mmm ... indeed that looks like a much better solution than the pre-made xci.
<_florent_> In fact in the initial version, the initial PHY was slightly modified to expose the second QPLL from the to the user and allow it's use for other protocol, so it was not manually generated. But this is no longer used and this is generally too complex to mix PCIe and other protocol on the same Quad, so it's indeed better now to just generate PHY from the tcl.
<_florent_> I don't think doing something similar for Ultrascale will be too complicated, I could have a look when I'll have a bit more time.
<_florent_> paultech: Most of the developpers are probably using the Arty A7, so it's possible there are some issue on the Arty S7 with SPI Flash. Feel free to open LiteX-Boards issue/PR if you think you fixed some parts.
<paultech> I will do, just ensuring I don't break more than I fix. I've been around FPGA's plenty but this is my first exposure to ground-up development with them so still building my board collection.
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