_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<yootis> Has anyone here had luck using litescope over PCIe?
<mithro> yootis: I assume that _florent_ has
<yootis> I assume so as well, but I also assume he's asleep :)
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<cr1901> Heads up: If your amaranth directory- the one that litex uses- is a symlink to a copy of the amaranth repo, you may have trouble removing the old nmigen packages using pip 1/3
<cr1901> If you do "pip uninstall nmigen" or similar, and get ".egg-links were moved" and/or "no files left to uninstall"
<cr1901> You need to remove the nmigen*.egg-links manually from /lib/python/site-packages/ and amaranth's source root
<cr1901> ditto for amaranth-soc,stdio,boards
<cr1901> Your nmigen imports should still work fine w/o a stale copy of the nmigen packages lying around
<cr1901> /end
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<_florent_> yootis: Just read your mail, the issue seems related to mmap, can you try to specify the length of BAR0 here instread of 0:
<_florent_> Can you also provide the Linux distro you are using?
<yootis> fedora 34
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<cr1901> I've never tried... does the PCIe Xilinx stuff in principle work on Windows?
<tnt> Xilinx provides a win driver for their pcie dma stuff. AFAIK.
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<yootis> How do I figure out the size of the BAR?
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<SpaceCoaster> Snickerdoodle resurrected and bitstream built! https://github.com/enjoy-digital/litex/issues/601
<SpaceCoaster> I commented out i_USB0_VBUS_PWRFAULT = 0 in zynq7000/core.pay to get it to build. I am using a minimal zynq processing system block design, maybe too minimal.
<SpaceCoaster> Snickerdoodle has no serial, switches, leds so a blank slate but the bitstream builds.
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<tnt> yootis: lspci -v
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<SpaceCoaster> It blinks!
<yootis> _florent_ that doesn't help, the BAR size is 1M and setting it to 1M gives the same error. It is asking for 4026531848 bytes, which seems wrong.
<tnt> yootis: does pcie comms work otherwise ? litepcie_util read the correct id string etc ?
<yootis> yes
<yootis> the only thing I can't get to work is litescope
<yootis> Actually, maybe I'm nuts. I copied the docs where it says how to add the analyzer, but how does it know whether to connect it to PCIe or JTAG?