_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> nickoe: --safe mode with litex_term will indeed be slower (since disabling multiple outstanding frames), that's possible we can avoid it in your case, but loading binaries over litex_term in simulation will always be slower than direct initialization of memory (which is possible in simulation but not on hardware). So for fast initialization without .json support currently implemented, you can use a simple script to pre-generate
<_florent_> the .bin file you want to use.
<_florent_> nickoe: BTW, this is open-source, feel free to modify/hack code until developers have time implementing the feature :)
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<nickoe> _florent_: Ok, I will try that. I have seen that section, but I think I never really tried it as a replacement. Yeah, but I am still learning, so I am mostly asking to make sure I don't fukaround with something that is alread made as it should be .
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<nickoe> _florent_: It does not appear to run after lift off. I did veryfy that the first couple of bytes at 0x40000000 do appear to be from the demo.bin
<nickoe> :S
<nickoe> When not adding soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"]) and it just boots to bios initially.
<nickoe> so boot 0x40000000 does not work in this case.
<nickoe> and the value in soc.mem_map["main_ram"] is 0x40000000
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