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<tcal>
tnt: that fixed it!!!
<tnt>
tcal: \o/
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<leons>
I've got to say, compared to how crazy running a bit-bang memory mapped I2C over wishbone over UART through a TCP connection tunneled through two SSH sessions with a latency of ~10ms sounds like, it works surprisingly well. Essentially doing the thing outlined here https://twitter.com/enjoy_digital/status/1382032355351801861. Thanks _florent_ for providing the infrastructure for that!
<leons>
zyp: Awesome, thanks! It works like a charm and is also significantly faster than the other one (presumably because of the microsecond-sleep delays which really aren't needed when you bitbang over wishbone-uart-tcp-ssh :D)
<zyp>
it's not needed for bitbanging over wishbone-usb either
<zyp>
i2c is usually doing 400 kHz without issue, where a half clock is 1.25us, good luck getting latency below that from a python script running on a regular OS :)
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<leons>
yeah i figure 🙂
<leons>
oh my, I just found out I can tell Element to stop replacing my plain-text smileys with unicode emojis... not exactly a great idea to have that enabled by default :/
<bjonnh>
will it just require me to tweak some configs?
<tpw_rules>
i just cannot get lxterm to work properly. i'm trying linux-on-litex-vexriscv on my butterstick and i can use openocd to program the svf just fine. but lxterm just prints garbage. some letters on the keyboard echo a different letter back but it doesn't really make sense
<tpw_rules>
i get a blue pattern on the LEDs until lxterm starts then they shut off
<bjonnh>
(XC7Z020-1CLG400C)
<bjonnh>
I see that there are some XC7Z020 supported
<tpb>
Title: Warn : gdb services need one or more targets defined __ _ __ - Pastebin.com (at pastebin.com)
<_florent_>
tpw_rules: and it was OK with the MT41K256M16?
<_florent_>
Can you try to increase the sys_clk_freq to 75MHz?
<tpw_rules>
idk, i didn't try it with that. my board only has the MT41K64M16 chip
<tpw_rules>
let me try with just the commands you listed
<_florent_>
ok, I'm just trying to understand, but on my side I was testing with a 8gb version
<tpw_rules>
hm, the problem is with linux-on-litex-vexriscv specifically
<tpw_rules>
(which runs at 60MHz)
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<tpw_rules>
ok, i tried rebuilding the linux-on-litex-vexriscv at 75MHz and it didn't help
<_florent_>
tpw_rules: you could eventually try to build by adding this: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/make.py#L377 (we saw issue with DM support on ECP5, which is used by SMP, using the l2 cache avoid using DM and could solve the issue if this the same thing we saw on OrangeCrab/ECPIX-5)
<tpw_rules>
does the l2 cache size make a difference?