_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<thirtythreeforty> Migen question: I need some unique identifier for the clock domain that a module will end up being clocked by. How should I do this? Things I've tried:
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<thirtythreeforty> - Ask the module to keep hold of it as self.clk or whatever. This does not work because strings like 'sys' are not unique until .finalize() is finished.
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<thirtythreeforty> (and in fact 'sys' might get renamed for a variety of reasons, so...)
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<thirtythreeforty> - Have a ClockSignal() in the module in question. ClockSignal's self.clk *will* be updated by the visitor when ClockDomainsRenamer walks the tree. This is better, because now I can get the real clock domain from the module after .finalize()
<thirtythreeforty> but, this still doesn't work because eventually the module doing the walking (via xdir()) must also be a submodule, and *its siblings* will not be finalized by the time the walker's do_finalize() is running, so the same caveat about 'sys' not being the real clock domain still applies
<thirtythreeforty> So, what to do? The ultimate goal is to learn which clock each module is using so I can connect it to the appropriately-clocked bus
<thirtythreeforty> (Also, is this easier in nMigen?)
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<_florent_> thirtythreeforty: I'm not sure to understand correctly your question, but for this, I would probably do the opposite: Have a clock domain in the submodule, expose it and clock the logic with this clock domain. Then at the top, connect the clocks of each submodule. In fact in a way very similar to traditional (S) Verilog/VHDL designs.
<_florent_> thirtythreeforty: if this is not answering your question, can you create an issue in LiteX to discuss this and share minimal code of what you are trying to do?
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<paultech> Looks like nMigen is now called Amaranth? Seems to have broken a few things:(
<tpb> Title: Creating Serdes0Measuring Serdes0 frequencies...TX freq: 153.903MHzRX f - Pastebin.com (at pastebin.com)
<tnt> paultech: :/ I hate name changes
<tnt> _florent_: so that looks like good news ?
<paultech> Yeah this one seems fairly intrusive. Changed repo URL, changed default branch, changed folder structure
<tnt> _florent_: Or possibly not ... works even without --loopback which it should definitely not ...
<paultech> Should litex_setup support different branches? Seems to be master only atm
<paultech> Took all of 10 seconds.   clone="recursive",branch="main") but unsure if breaking some convention if everything else uses master
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<paultech> Python package is also amaranth-yosys now, broke ci. How rude
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<tnt> So looks like the "tx freq is at 122.88" (the measured one in the pastebin above is bad because of measurement imprecision since litex_server is remote though vpn and forwarded ports etc ...).
<tnt> and the rx freq is actually 0 ...
<tnt> So that's obviously not good.
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<tnt> Any clue how to debug ?
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<whitequark> hey folks, I know the nMigen to Amaranth name change was going to break a few things
<whitequark> I'd be happy to assist in fixing the breakage
<cr1901> cc: paultech, I posted the log into #amaranth-lang with your msgs highlighted. I have no idea why CI broke
<cr1901> but I have some symlinks and program settings that depend on the old nmigen name, and I'd rather wait to break those settings until litex has handled the name change
<paultech> cr1901, whitequark, Don't think anything is broken on litex side yet. The setup script broke due to lack of a master branch but since remaining packages are still available I believe litex CI will build (apart from the previously mentioned failure with the setup script)
<paultech> Will leave that to _florent_to test out
<_florent_> Hi whitequark, thanks for letting us know, nice new name! The breakage should be limited and easy to fix for LiteX. I'll have a closer look in the next days.
<_florent_> tnt: the first thing to look at is the TX/RX initialization, the TX/RX freqs
<_florent_> tnt: so maybe you could add LiteScope and verify the TX/RX initialization FSM
<tnt> The TX freq looks fine. RX freq is zero. rx_ready stays at 0. I'm digging into the RX init fsm right now.
<tnt> I've never used litescope actually, no idea how that works.
<_florent_> and since you probably already have a UARTBone bridge in your design, it will be even easier
<_florent_> Just add the analyzer
<tnt> Why is litescope repo a github template ?
<_florent_> and you can use litescope_cli over the same litex_server that you are currently using for test_prbs.py
<tnt> Thanks for the howto, got it added with a few signals related to rx init status.
<tnt> (easy indeed, nice :)
<_florent_> litescope repo a github template ? Sorry, not sure to understand
<tnt> It says "public template" and "Use this template" instead of the normal clone button.
<_florent_> whitequark: Thanks!
<_florent_> tnt: Thanks, this is fixed (LiteScope public template)
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<tnt> Looks like RXRESETDONE never comes up.
<tnt> There is a RX clock ( RXOUTCLK ), it's just that because the init never finishes, it stays in reset.
<MoeIcenowy> how could I connect a FPGA's internal flash (co-packaged SPI Flash, accessible as a blackbox HDL module) to LiteSPI?
<MoeIcenowy> how should I construct the pads needed by LiteSPIPHY, make them connect to a Instance of the blackbox HDL
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<MoeIcenowy> I now created a Record and use them as the signals connected to the Instance and pass it as pads to LiteSPIPHY
<tnt> _florent_: mmm ... looks like the 1ms timeout in the init time machine was too short, it just kept resetting before it was done going through its internal init.
<tnt> Looking at the wait timer value, it seems to have taken ever so slightly above 2 ms.
<tnt> And now if I have the loopback disabled, I have tons of errors (kind of expected) and if it's enabled, no errors.
<MoeIcenowy> https://paste.aosc.io/paste/Rk3AbVJ0I0By9W1YKhbsPw my current try to connect LiteSPI flash to the blackbox
<tpb> Title: Pastebin | AOSC Pastebin (at paste.aosc.io)
<tnt> MoeIcenowy: and that doesn't work ?
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<MoeIcenowy> tnt: that does not work...
<MoeIcenowy> things do not get connected
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<tnt> MoeIcenowy: did you look at the verilog output see what it did ?
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<_florent_> tnt: Great, init time is indeed different between type of transceiver, result of test_prbs seems good
<tnt> _florent_: I currently don't have an external loopback to test with, maybe next week.
<tnt> I checked the talisse adi chip doesn't have any loopback mode I can enable, but it does have a PRBS mode I can try.
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<shorne_> _florent_: I got the package, thank you
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