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<f_>
hi
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<Kwiboo>
f_: I did some tests on c2, had to make the changes you suggested and copied some code for rank01_same support, but get same issue you have, readl from memory return unexpected value, and trying to make a second readl will freeze the system
<f_>
second readl?
<Kwiboo>
the arm generic timer does not seem to work, so get_timer/udelay is not working, added following defines for CFG_SYS_TIMER_RATE 1000000 and CFG_SYS_TIMER_COUNTER 0xc1109988 to meson64.h and CONFIG_SYS_ARCH_TIMER is not set to defconfig to hack around (use timer_e)
<Kwiboo>
trying to read the value from dram a second time
<f_>
Kwiboo: It does seem to work
<f_>
try running udelay with a very big value
<Kwiboo>
I added multiple write and read to memory before "if (data != pattern)", 2-3 times, and on second read it just stalled/freeze until watchdog reset
<f_>
hm
<f_>
with multiple readls it "worked" just fine...
<f_>
s/readls/reads/
<f_>
Kwiboo: curious about which value do you get on first read though
<f_>
It seems to be always the same on my board, even after multiple resets
<f_>
>reading 0x1000000 returns -784017578
<f_>
^ I get the exact same value even after resets and on every cold boot
<Kwiboo>
yeah, seem to be same for me, but have seen multiple values depending on if I have modified anything in dram config: 2079227388 (dec) 4623fe3 (hex) 7bee7dfc (hex)
<f_>
hmm
<f_>
What have you modified? I seem to remember that behaviour too
<f_>
I think it was when modifying a PGCR register dump, not sure
<f_>
At this point I checked my code multiple times and so far haven't found anything that could cause the issue
<f_>
Could probably be get_timer not working?
<Kwiboo>
I do not think that is an issue, tested with both generic timer and one based on timer_e, no diff
<f_>
udelay works for sure
<f_>
get_timer, no idea
<f_>
Although I suspect udelay is internally using get_timer anyway
<f_>
Nope. It uses get_ticks()
<f_>
But get_timer uses that too
<f_>
While Amlogic uses a register
<f_>
I confirmed the issue isn't timer-related
<Kwiboo>
I am not sure what values I changed caused the readback value to change, may have been PGCR, let me compare and see what I have changed
<f_>
git diff is very handy :)
<Kwiboo>
DMC_DDR_CTRL, DDR0_ADDRMAP_1 and DDR0_ADDRMAP_4 also DDR0_PUB_PGCR2 and DDR0_PUB_DX* for rank01_same support
<f_>
DX*!
<Kwiboo>
witout adding the DDR0_PUB_DX* regs, my c2 got stuck in "Waiting for PGSR0, currently 0x81c001ff" loop
<f_>
Ah these
<f_>
PGSR0 is pretty well documented on other SoCs and its behaviour seems to match these other SoCs
<f_>
But yeah anything not 0x80000fff or 0xc0000fff means something failed or didn't init at all
<f_>
I know for sure the phy inits
<f_>
PGSR stands for PHY Generat Status Register, and it returns success...
<minute>
there's a S905X5?
<f_>
*General
<phh>
minute: it hasn't started producing yet
<phh>
got demoed just today or yesterday at IBC
<f_>
minute: A311D2 still not mainline and they're now going to release S905X5???
<f_>
(no pressure lol)
<f_>
Am still stuck at gxbb/gxl lol
<f_>
and perhaps soon, A311D
<f_>
(still gotta finish porting SPL to gxbb/gxl)
<f_>
"gotta reverse-engineer it all"
<f_>
Wouldn't be surprised if S905X5 is similar to other SoCs already released
<f_>
e.g. A311D2
<phh>
I see A311D2 already has the ""hdmi 2.1"" pipeline and av1, so yeah should be pretty similar
<minute>
phh: ah i see
<phh>
it has a newer-gen cpu and gpu
<phh>
from arm
<minute>
f_: a311d2 is still quite exciting though
<phh>
but i don't expect they changed internals
<minute>
more RAM
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* f_
looks at A311D2 datasheets
<f_>
that is, if I can find A311D2 datasheets
<f_>
Thanks Khadas <3
<f_>
one more datasheet downloaded to my disk
<f_>
Seems like they renamed the DMC_DDR_CTRL register and either moved some stuff away or poorly documented it instead of the usual copy-paste they do on datasheets
<f_>
ah no
<f_>
Same DMC_DDR_CTRL register
<f_>
just a different address and their docs are mostly copy-paste
<f_>
minute: seems like it can only take up to 4 GB, is that correct?
<f_>
Their datasheets are badly formatted though :P
<f_>
even more so in the case of the A311D2
<f_>
Such poor memory map documentation.....they did it better on the incomplete S905 datasheets.
<f_>
Let's see if we get to have S905X5 datasheets anytime soon
<minute>
f_: the a311d2 can use 8GB
<f_>
hah
<minute>
(at least that's what banana pi are offering)
<f_>
minute: That alone is proof that their datasheets are very poorly made