<
lvrp16>
f_[xmpp]: you cannot compare a site without JS with one that has JS. It maintains a constant connection to check notifications.
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f_>
lvrp16: honestly have no idea what it could be
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f_>
discourse runs fine on potatoes
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f_>
Discourse is pretty nice
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f_>
Now thinking about this idea: when I get U-Boot SPL working, I could probably run the same tests you run at the factory
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f_>
would be worth trying
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f_>
and second test would be putting kodi on one of these boards and, like, using it as an actual media center.
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f_>
Both would be nice to see how reliable it will perform.
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f_>
Enough talking! Let's continue.
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f_>
Honestly I don't think it'll be 100% reliable (probably) but it would still be nice to see how reliable can we expect it to be.
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f_>
>*** clk: 12288 MHz
***
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f_>
That's what it detects..obviously wrong
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f_>
it should detect 912 MHz
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f_>
and that will affect PHY init etc
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f_>
since they make use of that detected value
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f_>
>*** clk: 912 MHz
***
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f_>
But still, that wasn't the main issue
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f_>
Still returns funny numbers.
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f_>
Should perhaps push what I have?
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f_>
For once the datasheets are useful
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f_>
DMC_DDR_CTRL looks well-documented
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f_>
both in the S905 datasheet and S905X datasheet
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f_>
(in S905X you can also enable DDR4 there)
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* f_
on his way to hardcode the size to 512MB.
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f_>
Really makes you think....is that old dram init code incomplete?
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f_>
What's PPCFG?...
* f_
on his way to download every single leaked Amlogic datasheet available in the linux-meson.com wiki
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f_>
Nothing convincing
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f_>
Says bit 0 sets the DRAM to 16 bit
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f_>
but what do the other bits do?
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f_>
>p_ddr_set->t_pctl0_ppcfg = (0xF0 << 1);
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f_>
^ amlogic-bl2.git/plat/gxb/ddr/ddr.c ddr_pre_init
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