narmstrong changed the topic of #linux-amlogic to: Amlogic mainline kernel development discussion - our wiki http://linux-meson.com/ - ml linux-amlogic@lists.infradead.org - official channel moved from Freenode - publicly logged on https://libera.irclog.whitequark.org/linux-amlogic
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<f_> hi all...unfourtunately my server is having issues
<f_> So I'll be back once I figure out the issue..in the meantime, please don't connect to it (looks like a DDoS?)
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* f_ is still waiting for ssh to connect.
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<f_> Weird? http works fine
<lvrp16> Throw a potato at it. 🙃
<f_> ¯\_(ツ)_/¯
<f_> Doesn't look like a DDoS to me anymore
<f_> lvrp16: also try running whois on vitali64.duckdns.org
<f_> What's also pretty ironic is the fact that IIRC the lepotato is more powerful than my server (intentionnal)
<f_> I made the choice to *not* max out on specs
<f_> lvrp16: Also did you see that pmOS MR get merged?
<f_> but about your remark on outdated BL21/BL301...I'll create a MR when I have time, to merge all amlogic u-boot packages
<f_> *shell kicks in*
<lvrp16> I was sick the last three days so I haven't gotten quite up to speed on my emails yet.
<f_> Hope you're doing well now
<f_> It's fine
<lvrp16> Yeah doing fine. Just dealing with a headache so taking it easy.
<f_> Sure
<lvrp16> You took this far while I have been away though.
<f_> Not really
<f_> in your thread a pmOS maintainer asked if this was a blocker for the MR
<f_> (I said no, because it can be done in a later MR anyway, and it will be done)
<f_> and he merged it
<f_> anyway this is a VPS host problem
<f_> Let's get back to hacking
<f_> (git and ssh is sorta up and it's all that matters for now)
<f_> (it's just slow)
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<f_> (it's fast again)
<f_> (ok no)
<f_> getting back to hacking. It should get ok
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<alexeymrvz> Hi narmstrong ! Please, when you have free time, look at my small patch with fixes in SM driver (Linux): https://lore.kernel.org/all/20230830140850.17130-1-avromanov@salutedevices.com/
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<f_> lvrp16: by the way, wouldn't it be nice to see U-Boot SPL booting from SPI too?
<f_> (I'll get it to work at some point)
<lvrp16> Haha definitely. We will throw some engineering time at it as well after we launch stuff.
<f_> Honestly it shouldn't be too hard to get it to work..in theory
<f_> But getting lafrite to work in the first place implies modifying DRAM init
<f_> I don't think I need to modify it too much for lepotato to work, however (probably some registers got moved at different addresses)
<f_> But lafrite will probably need some adjustements
<f_> I'll see how much when I'll get to it, though.
<f_> I won't send that U-Boot SPL port until I get gxl to work too.
<f_> (signing side is already done, for all SoCs)
<f_> (thanks again Kwiboo )
<f_> Technically trying to get SPL to run on every single amlogic board on my desk
<f_> :)
<lvrp16> The DDR init code is not significantly obfuscated.
<f_> not obfuscated at all
<f_> so it should be easy to adapt changes
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<f_> Not even what ghidra's decompilation is obfuscated
<f_> s/what //
<f_> I did notice how BL2 tries multiple settings before it succeeds, on lepotato
<f_> It usually doesn't. It just chooses according to ddr_clk
<f_> so either that's new, or it has been around since gxbb
<f_> I'll check
<f_> It has been around since gxbb
<f_> According to my comments it's enabled when ddr_channel_set==CONFIG_DDR_CHL_AUTO
* f_ checks lepotato acs
<f_> >#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR_CHL_AUTO
<f_> Could probably implement this
<f_> I think that's one of the few mods they made, but it should be easy to reimplement
<f_> It's just trying again and again until it suceeds
<chewitt> the temptation will be to make it work faster with a specific board with specific (known) DDR chips
<f_> Yeah that's what I'm doing for now.
<chewitt> but over time you see drift in chip specs/yields so the 'auto' approach allows you to have a range of specs and find the one that works
<f_> You also see boards like lepotato which come in multiple RAM configs (2 GB vs 1 GB)
<chewitt> the board vendor then has the option to switch supplier based on cost/price and availability
<chewitt> (availability has been a major factor in recent times)
<f_> That's also a reason why CONFIG_DDR_CHL_AUTO could genuinely be useful
<f_> chewitt: By the way. CHL_AUTO only affects ddr_channel_set
<f_> It doesn't affect the actual timings
<chewitt> i'm sure there's a ton of tweakable tihngs here
<chewitt> good luck :)
<f_> I confirmed the DDR init code in the old sources seems to work
<f_> (a long time ago)
<f_> I'm essentially just rewriting in a cleaner/neater way
<f_> But yeah, thanks :)
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<lvrp16> I have no idea how to tune DDR, but last time I tried, any DDR3 could not go much faster than 912MHz.
<lvrp16> Either the trace design or my parameters are way off.
<lvrp16> That stuff is still black box to me at this point.
<lvrp16> I should take a course on DDR training.
<f_> If it works, don't touch it.
<f_> CONFIG_DDR_CLK is also 912MHz on my set-top box
<f_> (at least with the WeTek Play2 acs.bin)
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<f_> Also I noticed how amlogic devs keep putting parentheses everywhere as well as unnecessary stuff like `(0 << 29)`, especially when modifying ddrs in ddr_pre_init()
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<narmstrong> It must be code generated from excel sheets
<narmstrong> (And the excel sheet produced by an old tcl/tk script running the simulation tool on an old rhel 6 vm)
<f_> haha
<f_> At this point programming is creating excel sheets lol
<f_> They use Excel, I use Vim.
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