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10:20
<
f_ >
hi all...unfourtunately my server is having issues
10:21
<
f_ >
So I'll be back once I figure out the issue..in the meantime, please don't connect to it (looks like a DDoS?)
10:24
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10:24
* f_
is still waiting for ssh to connect.
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10:32
<
f_ >
Weird? http works fine
10:32
<
lvrp16 >
Throw a potato at it. 🙃
10:32
<
f_ >
Doesn't look like a DDoS to me anymore
10:33
<
f_ >
lvrp16: also try running whois on vitali64.duckdns.org
10:33
<
f_ >
What's also pretty ironic is the fact that IIRC the lepotato is more powerful than my server (intentionnal)
10:34
<
f_ >
I made the choice to
*not* max out on specs
10:35
<
f_ >
lvrp16: Also did you see that pmOS MR get merged?
10:35
<
f_ >
but about your remark on outdated BL21/BL301...I'll create a MR when I have time, to merge all amlogic u-boot packages
10:35
<
f_ >
*shell kicks in*
10:35
<
lvrp16 >
I was sick the last three days so I haven't gotten quite up to speed on my emails yet.
10:36
<
f_ >
Hope you're doing well now
10:36
<
lvrp16 >
Yeah doing fine. Just dealing with a headache so taking it easy.
10:37
<
lvrp16 >
You took this far while I have been away though.
10:39
<
f_ >
in your thread a pmOS maintainer asked if this was a blocker for the MR
10:39
<
f_ >
(I said no, because it can be done in a later MR anyway, and it will be done)
10:39
<
f_ >
and he merged it
10:39
<
f_ >
anyway this is a VPS host problem
10:39
<
f_ >
Let's get back to hacking
10:40
<
f_ >
(git and ssh is sorta up and it's all that matters for now)
10:40
<
f_ >
(it's just slow)
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10:43
<
f_ >
(it's fast again)
10:44
<
f_ >
getting back to hacking. It should get ok
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16:39
<
f_ >
lvrp16: by the way, wouldn't it be nice to see U-Boot SPL booting from SPI too?
16:40
<
f_ >
(I'll get it to work at some point)
16:41
<
lvrp16 >
Haha definitely. We will throw some engineering time at it as well after we launch stuff.
16:42
<
f_ >
Honestly it shouldn't be too hard to get it to work..in theory
16:42
<
f_ >
But getting lafrite to work in the first place implies modifying DRAM init
16:43
<
f_ >
I don't think I need to modify it too much for lepotato to work, however (probably some registers got moved at different addresses)
16:43
<
f_ >
But lafrite will probably need some adjustements
16:44
<
f_ >
I'll see how much when I'll get to it, though.
16:45
<
f_ >
I won't send that U-Boot SPL port until I get gxl to work too.
16:46
<
f_ >
(signing side is already done, for all SoCs)
16:46
<
f_ >
(thanks again Kwiboo )
16:48
<
f_ >
Technically trying to get SPL to run on every single amlogic board on my desk
16:48
<
lvrp16 >
The DDR init code is not significantly obfuscated.
16:48
<
f_ >
not obfuscated at all
16:49
<
f_ >
so it should be easy to adapt changes
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16:55
<
f_ >
Not even what ghidra's decompilation is obfuscated
17:02
<
f_ >
I did notice how BL2 tries multiple settings before it succeeds, on lepotato
17:02
<
f_ >
It usually doesn't. It just chooses according to ddr_clk
17:02
<
f_ >
so either that's new, or it has been around since gxbb
17:15
<
f_ >
It has been around since gxbb
17:16
<
f_ >
According to my comments it's enabled when ddr_channel_set==CONFIG_DDR_CHL_AUTO
17:16
* f_
checks lepotato acs
17:19
<
f_ >
>#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR_CHL_AUTO
17:22
<
f_ >
Could probably implement this
17:22
<
f_ >
I think that's one of the few mods they made, but it should be easy to reimplement
17:23
<
f_ >
It's just trying again and again until it suceeds
17:23
<
chewitt >
the temptation will be to make it work faster with a specific board with specific (known) DDR chips
17:24
<
f_ >
Yeah that's what I'm doing for now.
17:24
<
chewitt >
but over time you see drift in chip specs/yields so the 'auto' approach allows you to have a range of specs and find the one that works
17:25
<
f_ >
You also see boards like lepotato which come in multiple RAM configs (2 GB vs 1 GB)
17:25
<
chewitt >
the board vendor then has the option to switch supplier based on cost/price and availability
17:25
<
chewitt >
(availability has been a major factor in recent times)
17:26
<
f_ >
That's also a reason why CONFIG_DDR_CHL_AUTO could genuinely be useful
17:27
<
f_ >
chewitt: By the way. CHL_AUTO only affects ddr_channel_set
17:27
<
f_ >
It doesn't affect the actual timings
17:28
<
chewitt >
i'm sure there's a ton of tweakable tihngs here
17:28
<
chewitt >
good luck :)
17:28
<
f_ >
I confirmed the DDR init code in the old sources seems to work
17:29
<
f_ >
(a long time ago)
17:29
<
f_ >
I'm essentially just rewriting in a cleaner/neater way
17:29
<
f_ >
But yeah, thanks :)
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17:37
<
lvrp16 >
I have no idea how to tune DDR, but last time I tried, any DDR3 could not go much faster than 912MHz.
17:37
<
lvrp16 >
Either the trace design or my parameters are way off.
17:37
<
lvrp16 >
That stuff is still black box to me at this point.
17:38
<
lvrp16 >
I should take a course on DDR training.
17:39
<
f_ >
If it works, don't touch it.
17:40
<
f_ >
CONFIG_DDR_CLK is also 912MHz on my set-top box
17:40
<
f_ >
(at least with the WeTek Play2 acs.bin)
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17:48
<
f_ >
Also I noticed how amlogic devs keep putting parentheses everywhere as well as unnecessary stuff like `(0 << 29)`, especially when modifying ddrs in ddr_pre_init()
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18:00
<
narmstrong >
It must be code generated from excel sheets
18:01
<
narmstrong >
(And the excel sheet produced by an old tcl/tk script running the simulation tool on an old rhel 6 vm)
18:14
<
f_ >
At this point programming is creating excel sheets lol
18:15
<
f_ >
They use Excel, I use Vim.
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