#linux-amlogic on 2023-09-09 — irc logs at libera.irclog.whitequark.org

2021-06-01 12:24 narmstrong changed the topic of #linux-amlogic to: Amlogic mainline kernel development discussion - our wiki http://linux-meson.com/ - ml linux-amlogic@lists.infradead.org - official channel moved from Freenode - publicly logged on https://libera.irclog.whitequark.org/linux-amlogic

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03:56 <lvrp16> aeroraptor: haha like I said 98 although I am not sure about the interrupts line

03:57 <lvrp16> it should still be 108 per https://github.com/libre-computer-project/libretech-wiring-tool/blob/master/include/dt-bindings/interrupt-controller/meson-gic.h

03:57 <lvrp16> it could be PPS is using gpio_to_irq instead of using the actual interrupt described in the DT

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10:14 <f_> I should try making ldto work on postmarketOS..would be nice.

10:14 <f_> Especially for these boards, and for me :P

10:15 <f_> would make enabling SPI much easier.

10:15 <f_> TODO

10:15 <f_> lvrp16: Also something funny about postmarketOS

10:16 <f_> the name "postmarketOS" suggests that it's an aftermarket OS..the thing is, when FairPhone introduced the FP5, Luca Weiss (someone at FP) made a merge request adding support for it :P

10:17 <f_> so ironically postmarketOS supported the FP5 *before* it even became available...premarketOS

10:53 <f_> Let's get back to fixing up init

11:10 <f_> So if I understand correctly, the PHY inits successfully

11:10 <f_> 0xc0000fff seems to indicate success.

11:23 <f_> The problem must be DMC-related in this case.

11:24 <f_> This is where we enable regions in memory

11:36 <f_> I noticed something

11:36 <f_> On cold boot PGSR0 == 0x80000fff

11:36 <f_> On reboot PGSR == 0xc0000fff

11:40 <f_> luckily since it seems like the DRAMC has many siblings in other SoCs, supported by U-Boot SPL...I can try figuring out what exactly succeeded

11:40 <f_> (or failed)

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15:30 <f_> I modified something and now it fails to init the PHY!

15:31 <f_> PGSR0 == 0xc0000006

15:35 <f_> grepping for PGSR0 in the u-boot tree

15:36 <f_> https://git.vitali64.duckdns.org/misc/u-boot-kii-pro.git/tree/drivers/ram/k3-am654-ddrss.h

15:36 <f_> Told you!

15:36 <f_> https://git.vitali64.duckdns.org/misc/u-boot-kii-pro.git/tree/drivers/ram/k3-am654-ddrss.h#n932

15:36 <f_> >>> bin(0xc0000006)

15:36 <f_> '0b11000000000000000000000000000110'

15:37 <f_> bits 1 and 2 as well as bits 30 and 31..

15:37 <f_> Looking at this list of #define's

15:40 <f_> Seems to mean PGSR0_PLDONE | PGSR0_DCDONE | PGSR0_SRDERR | PGSR0_APLOCK

15:41 <f_> PLDONE means PLL lock done

15:41 <f_> DCDONE means DDL calibration done

15:43 <f_> ^ these are good

15:43 <f_> As for SRDERR and APLOCK..

15:44 <f_> SRDERR seems normal

15:44 <f_> (happens on cold boot)

15:46 <f_> But yeah no PGSR0_IDONE

15:46 <f_> (means init done)

15:47 <f_> So..PGSR0 doesn't seem to report any error

15:58 <f_> Ok so reverted whatever I did and it succeeds again

15:58 <f_> That PGSR0 register is really nice

16:01 <f_> One more SoC (H6/sun50i) uses a similar DRAM

16:05 <f_> So much SoCs to borrow documentation from!

16:15 <f_> sun6i dram code looks similar, too.

16:20 <f_> Especially the phy init code

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19:37 <f_> Note to myself: the address map might be wrong.

19:38 <f_> I'll go.

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