narmstrong changed the topic of #linux-amlogic to: Amlogic mainline kernel development discussion - our wiki http://linux-meson.com/ - ml linux-amlogic@lists.infradead.org - official channel moved from Freenode - publicly logged on https://libera.irclog.whitequark.org/linux-amlogic
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<wens> setting up hosting with proper access controls and all the bells and whistles, making sure it runs smoothly for everyone using it, hosting your own network and machines, is a whole different skill set that normal developers don't really have
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<f_> wens: I didn't have to deal with access controls?
<f_> Also you don't have to host your own network and machines
<f_> One single VPS is more than enough for a git server
<f_> No network required.
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<f_> Let's continue.
<f_> It can write but not read
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<f_> Time to look at the datasheet!
<f_> (am using the S905X datasheet as published by Khadas)
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<f_> The S905 datasheet is really imcomplete which is why I try to avoid using it as much as possible
<f_> Really thinking about the DMC being b0rked
<chewitt> jbrunet: ping!
<f_> The PGSR0 register seems to report success, probably
<chewitt> jbrunet: I'm working on a Linux 6.5.y patchset for LibreELEC .. previous (current) one is Linux 6.1.y
<f_> PGSR stands for PHY General Status Register
<chewitt> jbrunet: I'm seeing a possible regression with PCM audio on the AXG driver - I'm testing with an Odroid N2+
<f_> of course, not documented in the S905X datasheet, but it's documented in old sources.
<f_> I'll let chewitt talk :)
<chewitt> jbrunet: In Kodi I have audio output, but only in stereo
<chewitt> unless I enable pass-through audio, and then multi-channel output works
<chewitt> the same LE image on a GXBB device (so different driver) works fine with PCM multi-channel output
<f_> 6.5 is already out?
<chewitt> I'm looking at git history to see if there are any likely candidates, but no eureka moment yet, so wondering if you might have any ideas?
<f_> I should update the kernel used in pmOS for Amlogic devices :)
<f_> we're still at 6.4
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<f_> rebase the patches we apply, drop them if unnecessary...
<chewitt> jbrunet: for reference this is the current patchset https://github.com/chewitt/linux/commits/amlogic-6.5.y
<f_> Only two patches we apply are: 'ARM64: dts: meson-gxl: add support for the Xiaomi Mi Box 3' and 'add x96-mini support', both from exkc...
<f_> I wonder if they got applied now..
<f_> (all other amlogic devices we support run with no patches, e.g. lepotato and kii-pro)
<f_> chewitt: Doubt we support anything AXG though
<f_> (patches welcome though)
<chewitt> the AXG audio driver is used with G12A/B and SM1 boards .. so you probably do
<f_> Hm..
* f_ looks at pmOS wiki.
<f_> I don't think exkc got much working on any of the G12/SM1 set-top boxes we support
<f_> ah.
<f_> We don't support any G12/SM1 board whatsoever, with the exception of the X96 Air and X96 Max Plus, but support hasn't been merged yet.
<f_> Even then, audio seems to be broken on both
<f_> (MR is stale)
<f_> chewitt: so no, we don't (officially) support anything using the AXG audio driver
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<f_> anyway, upgrading the kernel has to go in my TODO list
<f_> (also includes upgrading BL21/BL301 for lepotato/lafrite and building them from source, on all boards as well as merging all U-Boot packages targeting Amlogic)
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<narmstrong> f_: there's not a lot AXG boards in the wild, and no sbc for sure
<f_> Perhaps one more reason why nobody bothered to support one of these AXG boards, in postmarketOS.
<narmstrong> yep
<narmstrong> they are used in small audio and iot stuff
<narmstrong> like smart speakers
<f_> Yeah I know.
<f_> The A in AXG means Audio right?
<lvrp16> I wonder how the acronyms are created.
<f_> GXBB stands for generation x baby right?
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<f_> As for GXL, the L remains a mystery.
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<f_> Aha.
<f_> RK3036 DRAM register names look very similar
<f_> >PCTL_DFIODTCFG
<f_> >PCTL_SCFG
<f_> That looks similar to me!
<f_> Additionally, sunxi boot0/boot1 DRAM init code looks similar!
<f_> The register names look very, VERY, similar
<f_> ^ compare this
<f_> ^ to these header files
<f_> ^ this, more specifically
<f_> Don't they look similar?
<f_> >Description: This file implements basic functions for AW1633 DRAM controller
<f_> So safe to say the S905's DRAM controller most likely has siblings in the RK3036 and sun6i!
<f_> Let's look at Allwinner's code for a bit.
<f_> Of course, Allwinner code quality™
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<f_> and, of course, Allwinner and Rockchip happen to use Synopsys DDRC!
<f_> Look at arch/arm/mach-sunxi/dram_sun6i.c
<f_> Doesn't that code look similar to Amlogic's code?
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<f_> Apart from, perhaps, different function names, that looks similar to me
<f_> Not quite the same, but similar.
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<f_> Interesting.
<f_> Of course, in Allwinner language, PCTL is called MCTL.
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<f_> That must be documented somewhere, but that also means we could borrow some of the docs the sunxi people have written to try and understand how the S905(X) DRAM works.
<f_> *try to understand
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<narmstrong> GXL is probably light, GXM is medium
<narmstrong> G12 is the 12th generation
<narmstrong> SM1 is the real mystery
<f_> SoMehow1
<narmstrong> GXL = Generation 10 Light
<chewitt> S4? .. T7?
<f_> narmstrong: By the way nice picture in the linux-meson website
<narmstrong> this is their new naming
<narmstrong> makes even less sense
<narmstrong> if it even made sense
<f_> this image
<f_> Who made this image
<narmstrong> thx
<narmstrong> I made it
<f_> Really nice and self-explanatory.
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<narmstrong> they made it interesting to have pin2pin compatible packages across different families
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<f_> means you can replace one SoC with another pin2pin compatible?
<f_> *another one that's...
<narmstrong> yes
<f_> lvrp16: BTW what happened to tartiflette?
<lvrp16> Lol @ generation x baby
<f_> G means generation
<f_> X means 10
<f_> GXBB is sometimes written as 'GXBaby'
<f_> so....generation x baby
<narmstrong> yep it was their first arm64 soc
<f_> I knew it!!
<f_> Also first SoC to use a fork of Arm TF-A
<narmstrong> they moved from an ARC SCP core and switched to TF-A so it was a big move
<f_> They were too late
<f_> S905 came out in 2015
<narmstrong> a little yes but at the same time plenty of chinese socs switches to armv8
<lvrp16> Tartiflette components have been sitting in our WH for 4 years.
<narmstrong> so I suspect ARM pushed them with a really cheap cortex-a53 license
<f_> Perhaps
<narmstrong> and mali
<lvrp16> Waiting for u-boot 2023.10 release before we do anything. Bandwidth limited on me.
<f_> Cottonwood will be the big one.
<lvrp16> After semi-launching La Frite, I needed the software to bake a while.
<lvrp16> Every time I rebased LOST on La Frite, it took a week and basically had to rewrite the whole thing.
<f_> BTW where's lost's source code?
<lvrp16> Not scalable across multiple boards so it was a waste to launch.
<lvrp16> Closed source 🤣
<f_> Why?
<lvrp16> Until I finished the pluggable architecture.
<f_> Then it will be libre?
<f_> Understandable
<narmstrong> BTW where's the upstream DT for cottonwood boards ???
<narmstrong> because so far I merged nothing :-p
<f_> BTW I saw many of your scripts being licensed under CC BY-NC (non-libre) and the portability script being licensed under CC-NC-ND (proprietary)
<lvrp16> Basically OS installation would be open source. But the driving components for LOST is SAAS based so not open source.
<f_> seems like you don't enforce the license on the portability script (you merged some PRs)
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<lvrp16> I am not terribly great with organizing licensing. I just shove them there willy nilly sometimes.
<f_> I'd recommend using a permissive license at the very least, for scripts
<f_> (copyleft doesn't make sense on scripts anyway)
<lvrp16> For all intents and purposes, public repos should all be open source.
<f_> My favourite permissive license is BSD-3-Clause
<lvrp16> I think that is part of GitHub's licensing requirement as well.
<f_> I don't care about GitHub :P
<f_> Never used it to host my stuff
<lvrp16> narmstrong: It seems ARM is reducing cost of A76 so we should see those pop up more.
<f_> I think more people should move to something other than github or gitlab..host their own git server, or join a public forgejo instance...
<lvrp16> I am an realist, not an idealist. 🤣
<f_> Know codeberg?
<lvrp16> Incremental impactful changes are better writing books.
<f_> (forgejo/gitea looks pretty similar to github tbh)
<lvrp16> IMHO. Everyone differs.
<f_> sure
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<f_> As far as github-like forges go, I highly recommend codeberg.org/forgejo/gitea
<f_> (if you ever wanted to move away from github)
<f_> A little off-topic here though :)
<f_> so I'll stop talking about git
<f_> lvrp16: but you could pretty much use 3BSD or MIT for your scripts. Both are pretty nice
<f_> GPL-3.0+ and MPL-2.0 are also fine.
<f_> (but who wants copyleft on scripts?)
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<f_> But the CC licenses you currently use on your scripts are not libre/open-source
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<lvrp16> I think the original policy was that everything to create the board bootloader, linux, and hardware integration was libre/open source to make a "libre" computer. All other value adds did not have to be depending on their complexity.
<f_> but still, code publicly available should be libre
<f_> Having a board that uses libre firmware to boot and a libre OS **by default** is really nice though, even better if it's mainline linux
<f_> (and mainline u-boot)
<lvrp16> That is already the case. We use upstream to the maximum extent but some tweaks just cannot go upstream. Neil, Jerome, and others did their level best.
<lvrp16> Again, theoretical vs real.
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<narmstrong> Intle hides all the tweaks in ACPI, easy :-p;
<lvrp16> Haha
<narmstrong> *Intel
<lvrp16> ACPIOS
<f_> MINIX/ME
<lvrp16> Lets call it for what it is.
<narmstrong> but vendors like Qcom are now moving critical stuff into firmwares
<narmstrong> like usb/pd & battery management
<f_> narmstrong: saw you were working on qcom too
<f_> nice
<f_> (I own qcom hardware so it's nice to see mainline running on those)
<lvrp16> narmstrong: I guess the thinking is people will break their hardware if they have source.
<f_> lvrp16: there's a reason as to why there that big all caps disclaimer on each and every libre license :P
<narmstrong> lvrp16: not necessarely, I think they want to be sure the devices won't burn (very complex modern batteries) and still passes usb4/usb-pd/thunderbolt certifications even with running an open source os
<lvrp16> Yeah it gets hairy when people have regulator control in their own hands with overclocks.
<lvrp16> At one point Armbian was running some high voltage and clocks on Allwinner and Rockchip boards copied from SDK trees.
<lvrp16> Amlogic was saved by the grace of their closed ATF implementation.
<narmstrong> until now :-p
<f_> lvrp16: "saved"
<lvrp16> Haha
<f_> It wasn't even saved lol
<f_> *they weren't
<f_> there was that old tree rotting around :P
<f_> and most of their code remained unchanged :P
<lvrp16> The hardware was. There were patches running 1.4V on the SoCs.
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<f_> would be nice to implement the rest of BL31 upstream
<f_> (and easy for newer SoCs)
<f_> lvrp16: IIRC you told me amlogic rebased on Carlo's work, right?
<f_> Ironically that makes it much easier to reverse-engineer
<lvrp16> I have no idea TBH.
<f_> you only have to reverse-engineer their mods ¯\_(ツ)_/¯
<f_> Even if it wasn't it's clearly based on TF-A
<lvrp16> They updated PSCI for me.
<narmstrong> lvrp16: on gxl ?
<lvrp16> narmstrong: yeah 1.0
<narmstrong> lvrp16: nice for system suspend/resume!
<lvrp16> Suspend, poweroff, resume all works within our tree.
<narmstrong> noice
<lvrp16> Noiceeeee
<f_> which tree?
<narmstrong> now runtime pm :-p
<lvrp16> Our linux/u-boot/blx.
<f_> Did BL2 get modified too?
<narmstrong> nop it's only the PSCI interface
<narmstrong> in bl31
<lvrp16> Yeah, although GXL boards are still missing a PMIC so suspend is not 0W.
<narmstrong> you don't want to deal with pmics :-p
<lvrp16> I know it needs a lot of firmware work but 0W power off is nice.
<f_> yeah sure
<f_> but have they done any mods on the bl2 binaries you're using?
<lvrp16> f_: no same bl2
<f_> Ok
<f_> I wonder if I can use the sun6i dram init codebase...
<f_> (with some mods, of course)
<f_> I could use it as documentation
<lvrp16> I know sunxi had someone do the timing window testing. It would be cool to have infrastructure to do DDR tuning based on that.
<lvrp16> Scroll down
<f_> Yeah you linked to this page before.
<narmstrong> They made a great work, really impressive
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<f_> Indeed
<f_> and that work will be useful for documenting the DRAM used by Amlogic!
<f_> aha!
<f_> Rockchip code looks like it could be useful too
<f_> explains a lot
<f_> >phy status1: c0000fff
<f_> ^ PGSR0 register dump
<f_> 0xc0000fff looks like it's failing
* f_ on his way to copy-paste debug("%s: %d: PGSR0: %x", __func__, __LINE__, readl(DDR0_PUB_PGSR0))
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<lvrp16> If I had the time, I would write some automation for playing with (LP)DDR settings. I trust the vendor stuff for only a baseline.
<lvrp16> I have been hitting a lot of issues with all the dynamic freq voltage memory controller drivers being upstreamed.
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<f_> \o _whitelogger
<f_> drivers/ram/k3-am654-ddrss.h looks interesting...
<f_> Even more similarities!
<f_> It's the TI AM654 DDRSS driver
<f_> What I'm specifically looking for, is what the PGSR0 errors mean
<f_> I almost want to mod BL2 for debugging purposes..
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<f_> ...
<f_> 0xc0000fff might indicate success?
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<aeroraptor> Hello everyone! I'm hoping someone can help me update a device tree source file to change a pin definition. This (should) be an easy change but I'm having trouble finding some of the necessary information.
<chewitt> f_ I googled "PGSR0 errors" and this is one of the first links:
<f_> And of course it throws an error 403 on me :/
<chewitt> there's an excel sheet there which might be useful
<aeroraptor> What I want to do is change it from using GPIOAO_7 to using GPIOCLK_0 (which is GPIO 98). From reading the s905x datasheet I believe that GPIOCLK_0 can be used as an interrupt, so I just need to swap out the pinctrl-o, gpios, and interrupts parameters. Right now I'm digging through in the example dts files to see if I can find anything else using GPIOCLK_0
<aeroraptor> which doesn't seem to have all of the information I need
<chewitt> I downloaded it and put it on DropBox ^
<aeroraptor> oh haha wrong person
<f_> I hate when people block Tor users for no reason..
<f_> (or when they use Cloudflare, which blocks Tor users)
<chewitt> DropBox or Ti ?
<f_> TI.
<f_> No idea if Dropbox blocks Tor
<chewitt> click the link and you'll find out..
<f_> That's what I did
<f_> It's slow.
<f_> but seems to work
<f_> (does it?)
<f_> It doesn't, let's once again fallback
<lvrp16> aeroraptor: look at the meson-gxl-gpio.h file.
<lvrp16> #define GPIOCLK_0 98
<lvrp16> But the gpio controller is not gpio_ao
<f_> I just noticed something funny
<f_> Some PCTL registers are documented in bl301
<aeroraptor> lvrp16: thanks, I actually just found that in the 1wire example dts they use this pin, and they have it in just &gpio "gpios = <&gpio GPIOCLK_0 GPIO_ACTIVE_HIGH>;"
<aeroraptor> so I have that part figured out
<f_> chewitt: I already downloaded it
<f_> Thanks
<f_> But it doesn't seem to contain much
<narmstrong> aeroraptor: you don’t need to set it as gpio to have is as interrupt
<aeroraptor> I'm just following the provided pps-gpio dts file they provide, which is working correctly
<lvrp16> chewitt: excel really?
<narmstrong> You get the number in the s905x datasheet
<f_> Glad sc-im supports excel files :)
<aeroraptor> narmstrong: okay, I can look there next. I also have to figure out two more things - pinctrl-o = <&spdif_out_ao_6_pins>; --- where are they getting this name? I can't find a table of these names anywhere
<lvrp16> aeroraptor: amlogic platforms before sm1 do not support double edged interrupts so do look for warnings in your kernel if you are attempting to use those.
<aeroraptor> I'm not, that shouldn't be a problem
<lvrp16> Clone the linux tree and grep
<f_> funny how many manufacturers host amlogic datasheets.
<narmstrong> aeroraptor: no need for a pinctrl either
<aeroraptor> okay so this sample provided by libre computer just has a lot of extra junk in it
<narmstrong> aeroraptor: the interrupt is always active whatever the pinctrl state
<aeroraptor> okay
<narmstrong> If you really want the pin to have a specific config (no enable, no pull up/down) use something like https://github.com/torvalds/linux/blob/a48fa7efaf1161c1c898931fe4c7f0070964233a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts#L34
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<aeroraptor> so GPIOCLK_0 is interrupt 108 - so I can define it as : interrupts = <&gpio_intc 108 IRQ_TYPE_EDGE_RISING>; ?
<lvrp16> 98
<lvrp16> Yes
<aeroraptor> it's GPIO 98 per the spreadsheet on google docs but per the datasheet it says 108?
<lvrp16> Oh sorry
<aeroraptor> no worries, just double checking. I've always been bad at device tree stuff
<lvrp16> We have an interrupt mapping header in the wiring tool.
<aeroraptor> maybe that's why the other example was written how it was
<narmstrong> You need interrupts-parent and then separately interrupts, or use interrupts-extended
<aeroraptor> gotcha, okay
<aeroraptor> it's not happy with me somewhere
<aeroraptor> line 13 is the interrupts line but it seems to be correct as far as I can tell?
<aeroraptor> the example code builds correctly so I know that part of the system is working
<aeroraptor> okay well I thought it didn't like the 108, but it doesn't like MESON_GIC_GXL_GPIOCLK_0 either
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<aeroraptor> also I just realized the example from github is not the one that was building successfully, it's this one from the libre computer forum
<aeroraptor> which seems to define the interrupt in yet another way
<aeroraptor> okay, well... this one built. I don't expect it to work.
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<aeroraptor> It took a lot of trial and error, but this works. the gpios entry IS required. https://www.irccloud.com/pastebin/AVBP7iOh/
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