<Kwiboo>
Some small findings: for some reason use of CONFIG_SYS_ARCH_TIMER stopped working, so I changed to use timer e, same as bl2
<Kwiboo>
reverted some of the newer values in ddr init, to match the one bl2 for c2 use, still seemed to work with newer values
<Kwiboo>
for some reason the dram size written into GX_AO_SEC_GP_CFG0 does not seem to stick, and instead reading it back in get_effective_memsize() returned 0, so use gd->ram_size as a workaround
<Kwiboo>
bl30.bin and bl301.bin must be running or bl31.bin will hang on aml_thermal_unknown() call
<Kwiboo>
bl31 for gxbb should probably switch to use bl31_params_parse_helper(arg0, NULL, &bl33_image_ep_info), instead of redefine gxbb_bl31_param that is an exact copy of the v1 params struct
<Kwiboo>
on gxbb (c2) BL2 seem to be started at EL1, on sm1 (c4) BL2 seem to already be started at EL3, so no need to ask BL1 to re-execute SPL in EL3
<Kwiboo>
skipping exception vectors and use of tiny mmc framework seem to save 6-7 kb
<Kwiboo>
ues of psci_system_reset in SPL seem to do nothing on gxbb, however on sm1 it triggers an exception loop, watchdog should probably be used to reset in SPL
<f_>
lvrp16, narmstrong, Kwiboo: honestly after you get DRAM to work everything else is trivial
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<lvrp16>
what's in BL30?
<f_>
Kwiboo: The reason why GX_AO_SEC_GP_CFG0 doesn't have the DRAM size is because nothing writes to it.
<f_>
lvrp16: no idea. Will probably be the next thing to reverse-engineer :D
<f_>
narmstrong: As for U-Boot SPL maintainership I'm available to maintain it
<lvrp16>
could really use this for g12 since the bootloader amlogic provides does not support anything but lz4
<lvrp16>
and the A311D stuff is at the boundary of what lz4 can fit in 1MB
<f_>
lvrp16: I guess you owe me a cottonwood lol
<f_>
SPL in g12 would be nice, indeed
<lvrp16>
we implemented lzma for u-boot, not fully merged
<f_>
As for gxl
<lvrp16>
but it's so fast and small
<lvrp16>
1MB becomes 0.5MB
<lvrp16>
1MB lz4*
<f_>
It's probably going to be easy to port lepotato, but porting lafrite will involve reversing DRAM init again
<f_>
but it should be doable :)
<lvrp16>
they're that different?
<f_>
lepotato uses DDR3 while lafrite uses DDR4 IIRC?
<lvrp16>
oh you mean DDR tuning support?
<f_>
yeah
<lvrp16>
does rockchip use the same controller?
<f_>
No, but it's still similar
<lvrp16>
saucha from pengutronix already did a number on that
<f_>
The SoC I found using the closest controller so far is Allwinner sun6i
<lvrp16>
rockhip rk3399's DRAM controller
<f_>
As for g12..i.MX8MQ
<f_>
ok. I'll write some upstreamable code for pll and power init
<f_>
power init is going to be easy. Just port bl21 code to SPL
<f_>
(or the old code but it remained mostly unchanged)
<f_>
Oh, power init is very simple
<lvrp16>
yeah it's a a few lines
<f_>
pll init...very simple to reimplement too
<f_>
Already did it once, then removed the entire code I wrote
<f_>
lol
<f_>
Kwiboo: I think BL30 and BL301 should be in the same binary
<lvrp16>
most of the clock setup is in the driver already so it makes things easier
<f_>
lvrp16: You're right!
<lvrp16>
about what?
<f_>
>most of the clock setup is in the driver already so it makes things easier
<lvrp16>
yes, when I was checking the suspend code, it was stupidly simple
<lvrp16>
and they power off the entire domain
<f_>
We really did a lot of progress yesterday :)
<f_>
just need to <del>send this upstream</del>
<f_>
I mean port to lepotato
<f_>
Would be nice to have gxbb+gxl support on the same patch series
<f_>
After that, just need to test how reliable it is
<Kwiboo>
f_: regarding GX_AO_SEC_GP_CFG0 do not retain any value is because we need to write to the SEC_AO_SEC_GP_CFG0 in sec address base
<f_>
Kwiboo: Yeah that's what I said above
<Kwiboo>
did not read all text yet :)
<f_>
I'll fix that myself. Just involves adding a writel somewhere
<f_>
Kwiboo: We did a nice work :)
<Kwiboo>
you already have it in dram_init, just wrong reg
<f_>
Indeed
<Kwiboo>
clrsetbits_32(SEC_AO_SEC_GP_CFG0, GX_AO_MEM_SIZE_MASK, CONFIG_DRAM_SIZE << GX_AO_MEM_SIZE_SHIFT); fixed it
<f_>
Thanks
<f_>
Indeed, wrong address base
<f_>
I checked just now
<f_>
The hard part should be over now
<f_>
(or was it already over yesterday? :) right?)
<Kwiboo>
f_: for bl30 and bl301 they need to be sent over mailbox as two separate binarys, guessing on gxl+ it is just a single bl30, should also be easy to pad and combine in binman
<narmstrong>
who's the user of the board id/hwid ?
<narmstrong>
all board I saw had the same as the reference design...
<Kwiboo>
found some random code that used hwid when I did a google/github search earlier, so probably nice to have it
<Kwiboo>
f_: Agree, we made great progress yeasterday, most hard parts are over, at least for gxbb :-)
<f_>
For gxl too..but it depends on which board we're talking about :)
<f_>
For lepotato it's probably going to be easy
<f_>
Signing is already done, thanks again btw
<f_>
Just need to implement support for one rank
<f_>
(should be easy)
<Kwiboo>
Only think I have an early revision of vim1 v12 in gxl family
* f_
throws a potato at Kwiboo
<f_>
VIM1 should be ok
<f_>
As long as it's gxl
<lvrp16>
f_: re cottonwood, we just got the units for KR/ER, probably can ship to you from Europe.
<f_>
Sure
<f_>
honestly if you shipped from china it wouldn't matter much to me
<f_>
I'm not that kind of person who eagerly waits for some SBC to arrive as fast as possible :)
<f_>
As long as it arrives, should be fine :)
<f_>
+ I don't need them *right now*
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<f_>
I wonder how SPL is supposed to load the SCP firmware
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<f_>
For some reason I keep getting synchronous aborts...
<f_>
esr 0x96000210
<f_>
followed by multiple other ones with esr 0x5e000000
<Kwiboo>
I did some more digging into size and combined bl30.bin+bl301.bin and it seem to depend on the bl30.bin on how it will depend, unfortenetly there have been multiple base address changes for bl301.bin, so the bl31+bl301 pair need to match :S