<Kwiboo>
remaining gd->ram_ props may also need to be set in you dram init
<Kwiboo>
ram_base, ram_top etc, not sure how core set these values. For Rockchip these values are set in rockchip specific spl/tpl code
* f_
looks at sun6i init code
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<Kwiboo>
your esr relate to: Abort caused by reading from memory, Alignment fault.
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<f_>
hmm
<f_>
0x1000000 is 4k-aligned though
<Kwiboo>
Probably the fdt code that tries to read a byte or similar, I have found https://esr.arm64.dev/?#0x96000021 usefull to get more details about the esr from exception
<Kwiboo>
Remember I had similar issue with unaligned read on rockchip, related to use of readb/writeb instead of readl/writel
<f_>
Either way it still can't read anything from DRAM :/
<f_>
Tried everything
<f_>
checked my code, multiple times
<f_>
Probably means my #define's are at fault? Doesn't look like it..the PHY successfully inits
<f_>
Didn't put much effort in the coding style though, when importing amlogic code
<f_>
(I know why it resets multiple times though)
<f_>
(wrong channel setting)
<f_>
but it seemed to work.
<f_>
I'll go.
<f_>
Kwiboo: If you want try to compile this tree and simply replace the amlogic BL2 binary with your compiled binary, in the signing recipe
<f_>
and remove that sed command and anything bl21-related.
<f_>
well...
<f_>
you could also sign using amlimage
<f_>
it can't load anything anyway
<f_>
so...just use amlimage to sign that compiled binary, run.
<f_>
See you soon!
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<narmstrong>
f_: ok it looks improbable pll isn’t initiallized and indeed pll_init() is called from bl2_arch_setup() so you need to init pll before init ddr otherwise the bus clocks will be too slow for the parameters you set in the ddr controller