narmstrong changed the topic of #linux-amlogic to: Amlogic mainline kernel development discussion - our wiki http://linux-meson.com/ - ml linux-amlogic@lists.infradead.org - official channel moved from Freenode - publicly logged on https://libera.irclog.whitequark.org/linux-amlogic
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<lvrp16> f_[xmpp]: yeah there's a lot of stuff being presented at ER, gonna be a fun and interesting conference
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<f_> hi all
<f_> lvrp16: Have UCM2 profiles?
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<f_> Haha
<f_> >dram: 7 MB
<f_> that.....explains a lot
<f_> or I might have made a miskate when printing out the size
<f_> >dram: 2048 MB
<f_> Yeah I made a mistake when printing
<f_> fdt_path_offset(gd->fdt_blob, "/memory");
<f_> ^ this is causing issues
<Kwiboo> f_: Nice progress!
<Kwiboo> Guesing the existing dram_init() is not really valid for SPL
<f_> I actually just copy-pasted the existing one into the new one
<f_> after actual init
<Kwiboo> guess you only need to set gd->ram_size, and since you print 'dram: 2048 MB' you already have correct value?
<f_> ^ full log
<f_> Kwiboo: I guess so
<Kwiboo> remaining gd->ram_ props may also need to be set in you dram init
<Kwiboo> ram_base, ram_top etc, not sure how core set these values. For Rockchip these values are set in rockchip specific spl/tpl code
* f_ looks at sun6i init code
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<Kwiboo> your esr relate to: Abort caused by reading from memory, Alignment fault.
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<f_> hmm
<f_> 0x1000000 is 4k-aligned though
<Kwiboo> Probably the fdt code that tries to read a byte or similar, I have found https://esr.arm64.dev/?#0x96000021 usefull to get more details about the esr from exception
<Kwiboo> Remember I had similar issue with unaligned read on rockchip, related to use of readb/writeb instead of readl/writel
<f_> Either way it still can't read anything from DRAM :/
<f_> Tried everything
<f_> checked my code, multiple times
<f_> Probably means my #define's are at fault? Doesn't look like it..the PHY successfully inits
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<Kwiboo> could be some clock that need to be configures? https://git.vitali64.duckdns.org/archive/amlogic-bl2.git/tree/plat/gxb/pll.c configure some
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<f_> Doubt it.
<f_> in my earlier tf-a BL2 adventures, when I imported all that old dram code it worked by just running the `ddr_init()` function
<f_> see https://git.vitali64.duckdns.org/misc/trustedfirmware-a.git/commit/?h=wip/gxbb&id=aaf0f79c79c9a0cf331ed1d49efdda93cb659cc0
<f_> Didn't put much effort in the coding style though, when importing amlogic code
<f_> (I know why it resets multiple times though)
<f_> (wrong channel setting)
<f_> but it seemed to work.
<f_> I'll go.
<f_> Kwiboo: If you want try to compile this tree and simply replace the amlogic BL2 binary with your compiled binary, in the signing recipe
<f_> and remove that sed command and anything bl21-related.
<f_> well...
<f_> you could also sign using amlimage
<f_> it can't load anything anyway
<f_> so...just use amlimage to sign that compiled binary, run.
<f_> See you soon!
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<narmstrong> f_: ok it looks improbable pll isn’t initiallized and indeed pll_init() is called from bl2_arch_setup() so you need to init pll before init ddr otherwise the bus clocks will be too slow for the parameters you set in the ddr controller
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