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<minute>
i have this weird issue still with bpi cm4 ethernet (a311d + RTL8211F) which never works on initial boot. dts was missing a reset for the phy (i think it should be GPIOZ_15). if i toggle this with gpioset and reboot, the phy most of the time works. but if i include it as reset-gpios in &ext_mdio, it fails
<minute>
with phy_poll_reset failed: -110 and __stmmac_open: Cannot attach to PHY (error: -110)
<minute>
Kwiboo: argh, that sounds nasty... but thank you for pointing it out
<f_>
I have exactly 2 rockchip sbcs
<Kwiboo>
minute: yeah, there is possible double trouble, first phy device may not be created, and second reset_gpio pin is only deasserted (and not asserted prior to that) when linux issue a reset on the phy
<Kwiboo>
it should at least try to do it when CONFIG_DM_ETH_PHY is enabled
<minute>
Kwiboo: if i do the legacy method with snps,reset-gpio, i always get __stmmac_open: Cannot attach to PHY (error: -19)
<f_>
argh. ghidra freaks out when I try to import amlogic header code
<f_>
I think it doesn't like Amlogic coding style lol
<f_>
Seeing how PLL init failed I kinda expect DRAM pll failing too.
<f_>
As for the DMC_DDR_CTRL changes, should still work in my case
<f_>
Bit 22 isn't used when the rank mode is set to using one rank
<f_>
(which is the case with *my* lepotato. Yours may differ depending on the ram configuration you chose)
<Kwiboo>
minute: try with snps,reset-delays-us = <0 20000 100000>; or similar, realtek doc mention: For a complete PHY reset, this pin must be asserted low for at least 10ms. Wait for a further 30ms before accessing the PHY register.
<f_>
Did I mention that gxl BL2 codebase is mostly the same as gxbb BL2 codebase?
<Kwiboo>
f_: great that you are making some progress on gxl :-)
<f_>
:)
<f_>
gxl shouldn't need much to boot
<f_>
Perhaps some fixes here and there.
<f_>
The hard part has been done while porting gxbb
<f_>
and I like how lepotato acs sources are available :)
<lvrp16>
f_: yeah it's nice :D
<lvrp16>
maybe could even add more ddr types :D
<f_>
I literally have multiple amlogic u-boot git repos cloned to my computer lol
<f_>
Could remove some now and stick with gxl
<f_>
lvrp16: BTW git email address is wrong I think
<f_>
unless you still have an email server @ libretech.co
<lvrp16>
It is correct.
<f_>
moreconfused.com
<f_>
Oh nice AML-A311D-CC acs sources are there too.
<f_>
And as always, timing.c is a huge mess. Thanks Amlogic!
<f_>
I'm sure that lepotato is more than happy to get U-Boot SPL :)
<minute>
Kwiboo: thanks, problem must be somewhere else though. i mean, i can fix the Phy not probing, but now i can't get any packets to be sent across
<minute>
i will first fix up uboot
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<minute>
hmm, so it seems random if the ethernet interface is in a "bad" or "good" state on boot
<minute>
the PHY-not-found issue is gone, but i'm back to a random roulette decision wether i can send packages over the interface or not
<minute>
packets
<minute>
aha, one has to remove and reload a whole stack of modules for this to work
<f_>
A311D MNT Reform is nigh!
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<minute>
so this works: 1. disabling ethernet in uboot dts. 2. in uboot: gpio clear periphs-banks15 3. linux driver will complain "cannot attach to PHY". 4. rmmod dwmac_meson8b dwmac_generic stmmac_platform stmmac mdio_mux_meson_g12a mdio_mux of_mdio; gpioset -D open-drain 0 15=1; modprobe mdio_mux_meson_g12a; modprobe dwmac_meson8b
<minute>
now the question: how to do this the clean way...
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