narmstrong changed the topic of #linux-amlogic to: Amlogic mainline kernel development discussion - our wiki http://linux-meson.com/ - ml linux-amlogic@lists.infradead.org - official channel moved from Freenode - publicly logged on https://libera.irclog.whitequark.org/linux-amlogic
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<minute> i have this weird issue still with bpi cm4 ethernet (a311d + RTL8211F) which never works on initial boot. dts was missing a reset for the phy (i think it should be GPIOZ_15). if i toggle this with gpioset and reboot, the phy most of the time works. but if i include it as reset-gpios in &ext_mdio, it fails
<minute> with phy_poll_reset failed: -110 and __stmmac_open: Cannot attach to PHY (error: -110)
<minute> xdarklight: perhaps you have an idea?
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<f_> hexdump0815: Sure, no problem
<f_> This is where PLL init fails.
<f_> "fails"
<f_> It stays in the loop indefinitely
<f_> (and I modified it a little by looking at my gxl BL2 decomp..will upload soon)
<minute> hmm, if i do the reset manually and reload dwmac_meson8b, it oopses
<minute> in stmmac_mdio_read_c22+0x34/0x138
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<minute> rmmod dwmac_meson8b can also oops in phy_free_interrupt
<f_> RealTek adventures...
<minute> lets try toggling the reset line in uboot then
<f_> I seem to remember having to add some stuff in the DT for ethernet to work on my gxbb set-top box
<f_> (just copy-pasted from chewitt's WeTek patches)
<f_> But I doubt it has to do with your issue though...
<f_> minute: https://git.vitali64.duckdns.org/misc/u-boot-kii-pro.git/commit/?h=wip/kii-pro&id=66ba32c62142d52a0d91d7df5c428f83442e1885
<minute> f_: ah yeah, i actually tried something like this. but not with 1000000 delay.
<f_> But I never got oopses related to ethernet..
<f_> That's in U-Boot
<minute> the oopses are only when i play with un/loading the modules.
<f_> Sure
<f_> Might have found the issue
<f_> (going back to SPL)
<f_> chewitt: That's exactly what I did to have working ethernet on my board
<minute> chewitt: funny, i tried almost exactly this, but not with such a large delay, so will try that as well'
<f_> It was either that, or use hexdump0815's U-Boot builds chainloaded from vendor U-Boot
<f_> minute: I just copy-pasted :)
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<chewitt> I forget where the delay value came from
<chewitt> but knowing my skill level it was copy/pasted from somewhere :)
<f_> ¯\_(ツ)_/¯
<alexeymrvz> Hi narmstrong! Please take a look at the SM_UCLASS patch series: https://lore.kernel.org/all/20230921081346.22157-1-avromanov@salutedevices.com/. There is RvB from Simon Glass. Really sorry for the noise :)
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<f_> hm
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<narmstrong> alexeymrvz: sure no problem, sorry i was traveling last week and and off this week but I’ll do my best
<minute> also, weird that ETH_ACT_LED is on the same pin as ETH_NRST... sigh
<f_> The joys of working with Realtek hardware
<f_> let's see if PLL init in gxl works now
<f_> Great!
<f_> That was the issue!
<f_> Just need to fixup DRAM init now!
<f_> and it will be one more Amlogic SoC that can run U-Boot SPL as BL2 :D
<alexeymrvz> narmstrong thank you! Have a nice rest :)
<f_> Then it's going to be A311D
<minute> hmm [ 48.306860] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control rx/tx
<minute> ah, but now, no more packets
<minute> hmm, works after cold start
<f_> minute: Just needed to fiddle around with it :)
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<minute> lol, well i need to cool restart this a few more times to test...
<minute> sometimes it works just randomly
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<minute> yeah, seems to work now :0
<minute> reset-assert-us = <10000>;
<minute> reset-deassert-us = <1000000>;
<minute> reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
<minute> so, looks like GPIO_OPEN_DRAIN also made a difference
<f_> :D
<minute> tested a bunch more cold starts, works every time :D
<Kwiboo> minute: issue with ethernet phy reset is probably same issue that has been seen on rockchip, tried to sum it up in https://lore.kernel.org/all/47d55aca-bee6-810f-379f-9431649fefa6@kwiboo.se/
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<minute> Kwiboo: argh, that sounds nasty... but thank you for pointing it out
<f_> I have exactly 2 rockchip sbcs
<Kwiboo> minute: yeah, there is possible double trouble, first phy device may not be created, and second reset_gpio pin is only deasserted (and not asserted prior to that) when linux issue a reset on the phy
<Kwiboo> u-boot eth phy driver will at least reset the phy using a proper assert/deassert cycle: https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/net/eth-phy-uclass.c#L178-180
<Kwiboo> it should at least try to do it when CONFIG_DM_ETH_PHY is enabled
<minute> Kwiboo: if i do the legacy method with snps,reset-gpio, i always get __stmmac_open: Cannot attach to PHY (error: -19)
<f_> argh. ghidra freaks out when I try to import amlogic header code
<f_> I think it doesn't like Amlogic coding style lol
<f_> Seeing how PLL init failed I kinda expect DRAM pll failing too.
<f_> As for the DMC_DDR_CTRL changes, should still work in my case
<f_> Bit 22 isn't used when the rank mode is set to using one rank
<f_> (which is the case with *my* lepotato. Yours may differ depending on the ram configuration you chose)
<Kwiboo> minute: try with snps,reset-delays-us = <0 20000 100000>; or similar, realtek doc mention: For a complete PHY reset, this pin must be asserted low for at least 10ms. Wait for a further 30ms before accessing the PHY register.
<f_> Did I mention that gxl BL2 codebase is mostly the same as gxbb BL2 codebase?
<Kwiboo> f_: great that you are making some progress on gxl :-)
<f_> :)
<f_> gxl shouldn't need much to boot
<f_> Perhaps some fixes here and there.
<f_> The hard part has been done while porting gxbb
<f_> and I like how lepotato acs sources are available :)
<lvrp16> f_: yeah it's nice :D
<lvrp16> maybe could even add more ddr types :D
<f_> I literally have multiple amlogic u-boot git repos cloned to my computer lol
<f_> Could remove some now and stick with gxl
<f_> lvrp16: BTW git email address is wrong I think
<f_> unless you still have an email server @ libretech.co
<lvrp16> It is correct.
<f_> moreconfused.com
<f_> Oh nice AML-A311D-CC acs sources are there too.
<f_> And as always, timing.c is a huge mess. Thanks Amlogic!
<f_> I'm sure that lepotato is more than happy to get U-Boot SPL :)
<f_> hm got some diffs in ddr_init_pll
<f_> one new function: set_pll_ctrl(_new)
<f_> will it?
<f_> Nah it won't.
<f_> ARGH
<f_> They changed the register addresses!
<f_> The base address..it was 0xc8836000
<f_> it's now 0xc8837000...
* f_ double-checks in the datasheet
<f_> Indeed
<f_> I feel like I should clean up dram-gx.h
<minute> Kwiboo: thanks, problem must be somewhere else though. i mean, i can fix the Phy not probing, but now i can't get any packets to be sent across
<minute> i will first fix up uboot
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<minute> hmm, so it seems random if the ethernet interface is in a "bad" or "good" state on boot
<minute> the PHY-not-found issue is gone, but i'm back to a random roulette decision wether i can send packages over the interface or not
<minute> packets
<minute> aha, one has to remove and reload a whole stack of modules for this to work
<f_> A311D MNT Reform is nigh!
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<minute> so this works: 1. disabling ethernet in uboot dts. 2. in uboot: gpio clear periphs-banks15 3. linux driver will complain "cannot attach to PHY". 4. rmmod dwmac_meson8b dwmac_generic stmmac_platform stmmac mdio_mux_meson_g12a mdio_mux of_mdio; gpioset -D open-drain 0 15=1; modprobe mdio_mux_meson_g12a; modprobe dwmac_meson8b
<minute> now the question: how to do this the clean way...
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<lvrp16> what in the world...
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