narmstrong changed the topic of #linux-amlogic to: Amlogic mainline kernel development discussion - our wiki http://linux-meson.com/ - ml linux-amlogic@lists.infradead.org - official channel moved from Freenode - publicly logged on https://libera.irclog.whitequark.org/linux-amlogic
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<f_> hi
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<f_> https://git.vitali64.duckdns.org/misc/u-boot-kii-pro.git/commit/?h=wip/spl&id=ed9adeecdde62bf3b65af85e16111fa7bcd2f503
<f_> Time to modify register addresses for gxl
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<f_> Not sure what I can do for DDR0_PUB registers though :/
<f_> Completly undocumented
<f_> wondering if I should get an amlogic set-top box
<f_> for amlogic boards, lvrp16 got me covered for sure
<f_> hm
* f_ bookmarks this
<f_> Has more docs than what amlogic offers!
* f_ downloads this as a pdf
<f_> Still need to figure out the offsets though
<f_> lvrp16: Thanks!
<lvrp16> it may not be an exact match but at least you know what the registers do
<f_> Indeed. The SoC manufacturer is different so the registers won't be 100% the same.
<f_> Same for the base address, it's very much SoC-specific...
<lvrp16> f_: it would be very tedious for them to rewrite the DDR component in any significant way across all the similar socs
<f_> Of course
<lvrp16> the DDR controllers are not very sophisticated on these SoCs so it makes it easier
<lvrp16> cannot imagine the AMD/Intel controllers and the complexity around those
<lvrp16> since they're firmware driven rather than fixed
<f_> Good point.
<f_> I know someone reverse-engineering intel ram init blobs
<f_> they recently RE'd haswell mrc.bin
<lvrp16> that sounds like terrible fun
<f_> It is. They're really talented and smart.
<f_> I have a coreboot gerrit account as well :P
<f_> Used it exactly once and that was to add c-state 3 support to the MacBook2,1.
<f_> That is, when I was using a corebooted MacBook2,1 as my main computer :P
<lvrp16> I've never played with coreboot but I'll probably next year.
<f_> coreboot is really nice for sure, and the community around it is really awesome too.
<f_> It's useless though as it only does hw init. You also need a payload (e.g. TianoCore, SeaBIOS, linux)
<f_> hey, even grub can be used as a payload, and it has been done for a long time
<f_> My hp laptop isn't officially supported yet, and some people reported MXM GPU issues, either a message that makes you wait for 30 seconds coming from the VBIOS or no display
<f_> (there's a gerrit MR for it)
<f_> To ease using coreboot, there are coreboot distributions which offer ROMs ready to flash and use
<f_> For fun I tried sending SPL via USB: https://bin.vitali64.duckdns.org/65229ee2
<f_> It will panic() only after DRAM init though.
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<f_> Some PCTL registers will need trial and error :P
<f_> namely:
<f_> PCTL_POWSTAT, PCTL_POWCTL, PCTL_CMDTSTAT, and PCTL_CMDTSTATEN
<f_> oh, TREFI_MEM_DDR3 too.
<f_> (but it may probably have just been removed)
<f_> ah, nope.
<f_> it exists on lepotato acs
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<f_> https://git.vitali64.duckdns.org/misc/u-boot-kii-pro.git/commit/?h=wip/spl&id=d775f72c9840a07acbe86a8896952e41c51429eb
<f_> ^ just uses register offsets for calculating..implies just changing e.g. 4 to 1<<2
<f_> Time to test.
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<f_> gxbb still seems to work.
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