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<
f_ >
Time to modify register addresses for gxl
11:10
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11:12
<
f_ >
Not sure what I can do for DDR0_PUB registers though :/
11:23
<
f_ >
Completly undocumented
11:31
<
f_ >
wondering if I should get an amlogic set-top box
11:31
<
f_ >
for amlogic boards, lvrp16 got me covered for sure
11:44
* f_
bookmarks this
11:45
<
f_ >
Has more docs than what amlogic offers!
11:46
* f_
downloads this as a pdf
11:47
<
f_ >
Still need to figure out the offsets though
11:48
<
f_ >
lvrp16: Thanks!
11:48
<
lvrp16 >
it may not be an exact match but at least you know what the registers do
11:49
<
f_ >
Indeed. The SoC manufacturer is different so the registers won't be 100% the same.
11:50
<
f_ >
Same for the base address, it's very much SoC-specific...
11:54
<
lvrp16 >
f_: it would be very tedious for them to rewrite the DDR component in any significant way across all the similar socs
11:55
<
lvrp16 >
the DDR controllers are not very sophisticated on these SoCs so it makes it easier
11:55
<
lvrp16 >
cannot imagine the AMD/Intel controllers and the complexity around those
11:55
<
lvrp16 >
since they're firmware driven rather than fixed
12:02
<
f_ >
I know someone reverse-engineering intel ram init blobs
12:03
<
f_ >
they recently RE'd haswell mrc.bin
12:07
<
lvrp16 >
that sounds like terrible fun
12:07
<
f_ >
It is. They're really talented and smart.
12:11
<
f_ >
I have a coreboot gerrit account as well :P
12:11
<
f_ >
Used it exactly once and that was to add c-state 3 support to the MacBook2,1.
12:12
<
f_ >
That is, when I was using a corebooted MacBook2,1 as my main computer :P
12:15
<
lvrp16 >
I've never played with coreboot but I'll probably next year.
12:16
<
f_ >
coreboot is really nice for sure, and the community around it is really awesome too.
12:17
<
f_ >
It's useless though as it only does hw init. You also need a payload (e.g. TianoCore, SeaBIOS, linux)
12:17
<
f_ >
hey, even grub can be used as a payload, and it has been done for a long time
12:18
<
f_ >
My hp laptop isn't officially supported yet, and some people reported MXM GPU issues, either a message that makes you wait for 30 seconds coming from the VBIOS or no display
12:18
<
f_ >
(there's a gerrit MR for it)
12:20
<
f_ >
To ease using coreboot, there are coreboot distributions which offer ROMs ready to flash and use
12:22
<
f_ >
It will panic() only after DRAM init though.
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<
f_ >
Some PCTL registers will need trial and error :P
15:28
<
f_ >
PCTL_POWSTAT, PCTL_POWCTL, PCTL_CMDTSTAT, and PCTL_CMDTSTATEN
15:29
<
f_ >
oh, TREFI_MEM_DDR3 too.
15:29
<
f_ >
(but it may probably have just been removed)
15:29
<
f_ >
it exists on lepotato acs
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15:48
<
f_ >
^ just uses register offsets for calculating..implies just changing e.g. 4 to 1<<2
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<
f_ >
gxbb still seems to work.
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