10:17 <f_> hi all. I'm seriously considering stopping work on TF-A to instead port U-Boot SPL. What do y'all think about that?

11:16 <chewitt> f_ if I had a more serious clue about U-Boot I'd make an informed comment .. but sadly :)

11:16 <f_> Hi chewitt :)

11:17 <chewitt> btw, I saw in backlog that you don't have a g12 board for boot hacking

11:17 <f_> I mean, I could continue on tinkering with TF-A BL2 but have no idea if it's going to get merged upstream ¯\_(ツ)_/¯

11:17 <f_> chewitt: Nah I don't, sorta.

11:17 <f_> I do have a set-top box which might be g12 but it's not really mine.

11:18 <chewitt> if you're going to keep poking at things, feel free to purchase something locally and expense it to LibreELEC via our OpenCollective page

11:19 <f_> I should now have some gxl boards now though

11:20 <chewitt> what did you get?

11:20 <f_> lvrp16 sent me a lepotato and lafrite :)

11:20 <chewitt> ahh, nice

11:21 <f_> So I'll be able to work on gxl too, alongside or after working on gxbb.

11:23 <chewitt> usually the only way to find out if things will be merged, is to send RFC patches

11:23 <f_> There are some interesting g12 boards locally though, but even if I got one to poke at I would still finish working on gxl/gxbb first.

11:24 <f_> finish means, in this case, that I'm able to boot linux

11:24 <f_> I think I should at some point port LibreELEC to my KII Pro sometime.

11:25 <chewitt> i'm not sure what memory controller is used on the Allwinner boards, but I know Jernej Škrabec (one of LE's contributors) did work on U-Boot RAM init support for them

11:25 <f_> chewitt: 80% sure it's also a synopsys controller

11:26 <chewitt> he and others that have done work in that area can be found in the #linux-sunxi channel on oftc.net

11:26 <f_> At least that's what the linux-sunxi website states.

11:27 <f_> https://linux-sunxi.org/DRAM_Controller

11:27 <f_> https://linux-sunxi.org/A10_DRAM_Controller_Register_Guide

11:28 <f_> At least sun4i, sun5i and sun7i use a synopsys controller

11:31 <f_> Amlogic have put some comments in their code in their old sources.

11:32 <f_> With some trial and error and looking at these comments, I should probably be able to document how the controller works.

11:33 <f_> also by looking at ghidra...although Amlogic barely changed their entire BL2 code

11:34 <f_> chewitt: I'd say ~60%-70% of their code was kept unmodified.

11:36 <f_> e.g. if you compare storage_init() in my decomp and in their old sources you'll see that it was mostly kept unmodified, apart from some ghidra-related quirks.

11:56 <chewitt> "if it works, don't fix it" is a universal thing in a sources :)

11:57 <chewitt> in all..

11:57 <f_> Indeed.

11:58 <f_> As far as I can tell all they did to ddr init was adding LPDDR support

11:58 <f_> but that's pretty much about it.

14:12 <f_> I guess I could just sort of copy-paste Amlogic code and be done with it, but the long term solution would be to properly document registers.

15:53 <f_> Someone reached out to me saying that BL1/BL2/BL3* could have an option to "censor" UART logs. Is that true?

15:54 <f_> on gxl at least

15:58 <f_> s/true/a known feature/

16:05 <chewitt> ¯\_(ツ)_/¯

16:07 <f_> They dumped BL1 using Frédéric's amlogic-usbdl and found this: https://matrix.org/_matrix/media/v3/download/mozilla.org/6d8dcba5666e233a8c75835b29b18c9e8f6b10dc/image.png

16:08 <f_> (that person uses Matrix)

16:08 <f_> They fed the dump into ghidra and found this

16:08 <f_> In the meantime, in my BL2 decomp: https://git.vitali64.duckdns.org/misc/reversing-gxbb-bl2.git/tree/bl2.c#n7086

16:09 <f_> there's no such thing, which means they most likely added that in gxl and newer.

16:09 <f_> To confirm this I need to decompile gxl BL2 though

16:11 <chewitt> someone probably tried to 'tidy' the output and the reformatting function has unforeseen other potential

16:12 <f_> lol

16:12 <f_> Will feed gxl BL2 into ghidra real quick

16:27 <xdarklight> minute: it's good that you haven't tried my patch - it's obviously broken as I didn't zero-initialize "ret", meaning on successful rtw_sdio_read_port() calls it would return garbage. I'll send the proper patch as v2 to the mailing list and keep you Cc'ed. once you tested it please reply there (preferably with your Tested-by)

18:17 <xdarklight> minute: the patch is now in your inbox

19:39 <minute> xdarklight: ooooh ok thanks