<conchuod>
I think the problem is that the SBI implementation is so old that it's missing fixes for the emulation, so the misaligned access routines that've been in linux since the probing was added make it fail to boot.
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<lu_zero>
yet another cautionary tale for upstreaming as early as possible, I guess
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<LucasVella[m]>
I've read in many places that risc-v gives great importance to instruction fusion, and that there are preferred instruction sequences to facilitate fusion by the implementation. Can someone please point me to a document with listing the preferred sequences and the fusion opportunities?
<sorear>
there is no standard list of fused instruction sequences and no current effort to create one, llvm and gcc have lists of fusion sequences specific to specific cores that are enabled as part of -mtune
<sorear>
so you can look at the scheduler definitions - that's the closest thing we have to a central source of information
<sorear>
e.g. RISCVProcessors.td and RISCVMacroFusion.td
<sorear>
https://people.eecs.berkeley.edu/~krste/papers/EECS-2016-130.pdf has a bunch of speculation about possibly useful fusion pairs and is often cited by uninformed people, but (a) it has no standardization force (b) it does not describe any implementation which exists now or in the future (c) the design philosophy it advocates is directly opposite of what's currently being done for instance in the scalar efficiency WG
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<JohnHenry>
mengzhuo: thanks
<sorear>
i thought that one of the differences between v1 and v2 was that v1 had V 0.7.1 and v2 had V 1.0 but that can't be true if sg2042 has v2 and sg2042 has V 0.7.1
<sorear>
if sg2042 has c910 v2, then what version of c910 does sg2044 have?
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<Revy>
sg2044 is c920v2 / sg2042 is c920v1
<Revy>
c910v1 only has th1520.
<Revy>
mengzhuo said is incorrect
<Revy>
c920v1 is an IP delivered to customers and is the successor of c910v1
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<Revy>
th.sfence.vmas is not work on sg2042
<Revy>
it works on th1520
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<JohnHenry>
Revy: thank you too! do you know why it doesn't work? is there any documentation of that I can show my boss who wants me to get it to work?
<Revy>
cluster
<Revy>
th1520 core is in 1 cluster
<JohnHenry>
ah and th.sfence.vmas only broadcasts to the cluster of 4 cores
<JohnHenry>
Thank you Revy. If you come across a note anywhere from T-head / Sophgo that says that, please point me at it. :)