sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<courmisch> k1 microbenchmarks look suspiciously similar to C908. I guess they're based on the same design
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<sorear> vector? scalar? memory system? branch prediction? all of the above?
<sorear> iirc c908 is a single-issue in-order and there isn't a ton of flexibility there, MFD instruction latencies might differ
<courmisch> sorear: scalar looks almost the same, vector double speed
<courmisch> RDCYCLE is zeroed so that's from prorating RDTIME values, wide grain of NaCl apply
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<courmisch> are there any plans to runtime detect Zbb for libgcc bitops?
<sorear> i would be surprised. does libgcc even have the ability to make syscalls / awareness of the underlying OS?
<courmisch> aarch64 does it for LSE outlines
<courmisch> probing auxv in a high prio constructor. don't see why hwprobe couldn't be used
<conchuod> Today's linux next is panicing for me at __cpuhp_state_add_instance_cpuslocked :/
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<conchuod> Heh, did a bad bisection decided to go home and continue looking there, can't reproduce it here.
<conchuod> Seems to depend on toolchain version, llvm 17 doesn't crash and llvm 16 does.
<courmisch> that's going to be fuuuun
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<conchuod> It's a fun one too, cos the config has rust and cfi_clang - which causes a different panic :)
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<conchuod> palmer: low confidence bisection, but looks like c97bf629963e ("riscv: Fix text patching when IPI are used") is breaking boot for me under some conditions.
<palmer> ah, that's unfortunate
<conchuod> Gonna double check it and I'll send a mail.
<palmer> do you have anything more specific? nothing looks really wrong
<palmer> ya, cool, thanks
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<conchuod> I'm pretty low in confidence because it's not consistent nor is the backtrace the same each time.
<palmer> OK
<palmer> not sure if Alex is in here
<conchuod> dont think he is
<conchuod> palmer: here's one of the more common oopses
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<conchuod> palmer: reverted it on top of next/master and I'm now about 10 successful boots in.
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<ja_02> welcome
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<alexghiti> @conchuod: I'm looking into this, can I reproduce this on qemu? Or is it only on HW?
<conchuod> alexghiti: I only managed to reproduce it in hardware
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<alexghiti> Of course! So I may bother you a bit tomorrow if I need to test some fixes, I'll post them in the patch thread. Thanks in advance :)
<conchuod> I shut stuff down here cos I am too hot, I'll compile my .config etc for you tomorrow morning if needs be. Just lmk.
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<palmer> Thanks guys, I'll go merge other stuff... ;)
<conchuod> Oh no
<ja_02> ?
<conchuod> ja_02: sup?
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