<JohnHenry>
Older T-head cores like this Pioneer box I have can do a pretend-alike by using the T-head extension TLB-manipulation registers instead. Would upstream smile upon an assembly-alternative patch that implemented something like that but just for the T-head cores?
<JohnHenry>
I'm pretty new to all this Linux enablement stuff so I'm just trying to figure out where I can make a useful dent. :)
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<sorear>
skeptical, given the limited number of users, the limited benefit per user (you don't need it for correctness), and the lack of existing vendor-specific TLB support
<sorear>
I think there's a better case for supporting the T-head TLB broadcasting functionality as a replacement for IPI-based remote_sfence_vma
<JohnHenry>
Is there more to that story than Nobody's Enabled It?
<JohnHenry>
(the patch is flawed because it's using plain sfence.vma instead of the broadcast TLB invalidate)
<sorear>
I have no real idea why t-head does anything they do on the software side
<sorear>
if I understand the pdf manual correctly, there is no broadcast invalidate instruction, it changes the behavior of standard invalidate instructions depending on a bit in a M-mode register
<sorear>
which is a rather weird approach, either you need novel SBI calls for them (which is the original reason we use the SBI for remote fences - Berkeley wanted to allow for broadcast hardware without the complexity of an ISA extension) or you're permanently running a supervisor in a state where everything is broadcast?
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<JohnHenry>
Which manual are you reading? I didn't see anything like what you're describing and I certainly would like to.
<JohnHenry>
The broadcast instruction is SFENCE.VMAS on page 292. Reading it again, I wonder if it only hits the 4 cores in a cluster and not across the SG2042 NoC? Might just be a translation error.
<JohnHenry>
I'm guessing th.sfence.vmas is the same thing as sfence.vmas from the first manual except it says all harts. I don't know if that's a translation error or a real difference?
<JohnHenry>
Your story certainly makes the patch I thought was flawed make more sense tho.
<conchuod>
The SG2042 has a bunch of kinda concerning hacks in their kernel code IIRC, I really hope many of them are not needed for mainline.
<JohnHenry>
Could you point at one or two for me? I'm curious what you mean.
<JohnHenry>
FWIW I'm a master's student in computer architecture working on TLB coherence so the opinions of kernel folks are quite important to me.
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<JohnHenry>
and I need all the help I can get navigating all the various trees and patchworks and repositories
<JohnHenry>
thank you very much, I see what you mean
<JohnHenry>
that double-fence is painful to look at
<conchuod>
I have a pioneer, but I've not managed to actually build a kernel on the thing to replace the vendor one cos the nvme drive is too small!
<conchuod>
I also suspect the userspace would need to be replaced cos it'll be built for v0.7
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<JohnHenry>
I haven't native-build, just cross-compiled the sophgo kernel, but that worked!
<JohnHenry>
I'm interested in replacing the Fedora 38 it came with. We want to use upstream gcc with the xtheadvector for teaching, but I'm not sure what the best way to go about that stuff is
<conchuod>
JohnHenry: I think my take on adding something for that vendor version of svinval is similar to sorear's. There's no pressing need for it, and may be a very limited number of devices that it would actually benefit (is it just the limited number sg2042s?).
<JohnHenry>
Ah yes. I can't read Mandarin so I didn't even try with that version.
<JohnHenry>
I got pointed at mhint.TLB_BROAD_DIS by Chen Pei when I emailed him to ask why that flawed-to-me patch that flawed-to-me didn't use th.sfence.vmas and he said I would need to be sure and "enable MHINT.TLB_BROAD_DIS"
<JohnHenry>
ahhh editing myself is hard
<sorear>
me neither, so I'm much more confident in the official translation
<sorear>
that email reply implies that TLB_BROAD_DIS enables the sfence.vmas instruction instead of changing the behavior of sfence.vma, which makes far more sense but contradicts the manual
<JohnHenry>
the one I'm reading has a lot of confusing parts, like how the A-bit is set in a page table entry?
<JohnHenry>
does it trip a fault? does the page table walker do it?
<JohnHenry>
I can't find where the fault is handled and the A-bit is set so I'm assuming it's the hardware page table walker, but I'm a newb.
<sorear>
there's a requirement in the privileged spec that OSes have to handle hardware that throws a page fault if A=0, and §6.2.3 seems to say t-head takes that approach "the leaf page table is found but the access type does not conform to the setting of the A/D/X/W/R/U bit"
<JohnHenry>
conchuod: Thanks. That makes sense to me. I'm not sure how broadly applied and uniform the T-Head extensions are. If they apply to th1520 too, then there's probably a better case for doing some of these enablements?
<sorear>
afaik th1520 and sg2042 have exactly the same cores with the same extensions
<JohnHenry>
sorear: yes, so the apparent contradiction is giving me some pause. What I want to do is enable the hardware TLB invalidate and benchmark against vanilla and then benchmark against something like Nadav Amit's Page Access Tracking
<JohnHenry>
that I'd have to implement myself
<sorear>
what contradiction
<JohnHenry>
the email reply implying that TLB_BROAD_DIS enables sfence.vmas instead of changing sfence.vma
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<JohnHenry>
Did you run the Mandarin manual through machine translation to figure out that idea about sfence.vma being modified by TLB_BROAD_DIS? The part where the patch and you seem to have the same idea but the email reply and the manual disagree is making me think I've missed something crucial somewhere.
<sorear>
yes
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