03:19 <Loant> Is there list of commercially available/buyable RISC-V cores?

03:59 <palmer> I'm going to skip tomorrow morning, I've got a cold and I'm pretty much just sleeping all day...

04:37 <jacklsw> got riscv event?

05:26 <JohnHenry> I have recently acquired a Milk-V Pioneer with SG2042. Has anyone heard of using the th.sfence.vmas instruction for no-IPI TLB shootdown or played with the various TLB-manipulation registers on T-Head cores? I'm looking for some guidance as I noodle about thinking about trying to make kernel improvements.

06:39 <JohnHenry> The couple patches I can find from T-Head folks appear to be flawed or possibly incomplete: https://github.com/XUANTIE-RV/linux/commit/a08f2e5ff2a7e1911f4096b9519ebcd3366a60cc still uses plain old sfence.vma instead of th.sfence.vmas (called sfence.vmas before t-head standardized their extension instructions under th.) This one is interesting but

06:39 <JohnHenry> I'm not sure exactly what it's doing yet: https://github.com/XUANTIE-RV/linux/commit/ab72e26c518b453e153145e233db9f6edc88daae

06:40 <JohnHenry> So far it's the only patch I've found that twiddles smir/smel/smeh/smcir

11:13 <conchuod> palmer: I'll prob show up anyway, see if I Alex is around.

11:13 <conchuod> Or Andy, had a question for him too.

14:15 <drewfustini> palmer: hope you feel better soon!