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<la_mettrie>
hmm... i have an older mainline dtb for jh7110 which seems to have a pcie device (starfive,jh7110-pcie) but currently pcie seems to be missing from mainline's jh7110 device tree files. and there's no pcie driver in the kernel sources either, just pcie-phy drivers. wonder what's going on
<drmpeg>
Should be merged in 6.11
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<sorear>
I don't remember most of the details there
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<palmer>
OK, do you want someone else to pick it up?
<palmer>
no big deal if you do, people just usually wait for the original poster to resend as it's kind of stepping on someone's toes to just pick stuff up
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<courmisch>
is it just me or VSETVL is a lot slower than VSETVLI (for the same vector type)
<sorear>
surely that depends on the uarch, although we had a conversation about this a couple months ago
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<dzaima[m]>
sounds plausible; I'd be curious on more specific timings (also relatedly I wouldn't be surprised if vsetvli with vl=0 were similarly much slower)
<courmisch>
I checked on TH C908.
<courmisch>
sigh, that will imply a lot of duplicated code to specialize for different vector sizes
<dzaima[m]>
I'm imagining it being something like wanting to utilize register group size (for computing dependencies or whatever) before register values are known
<sorear>
the performance differences between different implementations of rvv are only going to get larger
<courmisch>
that's a compounding problem with tail-agnostic mode *not* short-circuiting needlessly long group multipliers
<sorear>
hopefully you didn't rewrite a large fraction on the rvv loops to dynamically generate vtype
<sorear>
do we know yet how either performs on x60?
<courmisch>
I tried two functions to see what it would do
<courmisch>
I can check, but measurements on X60 are much fuzzier as I haven't figured out how to allow RDCYCLE
<sorear>
does that matter after a few million iterations?
<sorear>
looks like 6 committed uses of vtype_(i)vli for dynamic vtypen generation
<sorear>
how soon are we expecting ooo + rvv? c920v2, x100, etc
<courmisch>
Yeah but now I'm trying on fixed-size functions, where using CTZ/CLZ at every entry isn't realistic
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<courmisch>
same problem on X60, it seems but the numbers are very coarse
<courmisch>
so only ways to optimise larger vector length will be to duplicate functions just to change the immediate vector types :(
<courmisch>
2x, 3x, 4x, 5x for VL=4, 8, 16 or 32 respectively
<courmisch>
well maybe we can ignore Zvl1024b for now
<sorear>
I was thinking "a few conditional branches and vsetvli instructions"
<courmisch>
well, if the function uses a single vector type, that should work
<sorear>
branch prediction is used millions of times more often than vsetvl and people ought to try harder
<courmisch>
unfortunately a large chunk of fixed-size functions use e8 and e16, or e16 and e32, or all three
<courmisch>
in this respect, the lack of signed-to-unsigned narrowing clip hurts
<sorear>
if you want to have a default implementation that assumes the core behaves sensibly with short vl, and then a separate implementation for c908 which uses hacked small lmul, that's only two versions
<sorear>
this ought to be in hwprobe but good luck getting any consensus on the semantics
<courmisch>
X60 has the same problem. In fact the problem came up with X60 - it works a lot better with halved LMULs compared to C908
<sorear>
signed to unsigned narrowing clip would be nice
<courmisch>
NEON has it, ahem cough cough
<courmisch>
it comes up all the damn time with video transforms
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