sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<naoki> oh I need to rebase defconfig patch...
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<naoki> ah, my defconfig patch doesn't conflict...
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<naoki> is linux-riscv ML is moderated? it seems my mail is brocked. I'm not a member of ML.
<naoki> oh no
<naoki> I sent wrong email address...
<naoki> please discard mails from naoki@milkv.com. correct address is naoki@milkv.io :(
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<Stat_headcrabed> conchuod: I just tried compiling newest git version of uboot+opensbi on debian 12. It just succeeded with no problem.
<naoki> ah my patch with correct address is appeared in ML and patchwork
<Stat_headcrabed> https://1drv.ms/u/s!AttKKQZrgnVagq4knz4FB2J4DFn6Vg?e=Oy7k3n
<Stat_headcrabed> Here is uboot binary compiled by myself
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<naoki> mmm, I'm a fool :(
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<conchuod> Stat_headcrabbed I'll grab my logs tonight. SPL didn't even print any logs
<conchuod> naoki: also, welcome. Good to have someone from milkv contributing
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<courmisch> now that B is ratified (Zba+Zbb+Zbs, no Zbc), should the kernel set bit 1 in hwcap when applicable'
<courmisch> ?
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<conchuod> I suppose it should
<conchuod> And set b in whatever other interfaces we have
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<LucasVella[m]> why did conventions end up being that in static programs jumps use auipc to load the address, but data uses lui?
<LucasVella[m]> everything else being equal, I would expect auipc to use more power
<sorear> data benefits from rematerialization (if you access the same global several times or in a loop, the lui can be hoisted), jumps don't in the simple case (you'd need to use a call-saved register, which means adding instructions to save it, which costs more than it benefits; interprocedural register allocation gets around this but isn't standard)
<sorear> there's also a long-standing tradition on almost all architectures that jumps and calls are always PC-relative
<sorear> simplifies linkers since R_RISCV_CALL relaxation only needs to handle the AUIPC + JALR case, no separate LUI + JALR case
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<LucasVella[m]> It makes no difference to whether lui or auipc is used to set the base address in the register for the purposes of hoisting.
<sorear> that's correct on every other architecture with an auipc-like instruction, but riscv's decision to use the _full_ PC instead of masking off the low 12 bits means that you can't have two auipc instructions in different places to generate the same value
<sorear> which greatly complicates what you can do with them in a compiler
<sorear> when I was working on the Go port a few years ago I wound up having it never hoist auipc instructions because there wasn't enough information in that pass to determine if the hoisted instruction would eventually need to be duplicated or spilled; gcc at the same time also never hoisted auipc, presumably for the same reason
<sorear> there are a lot more people working on gcc so they might have found a solution, that one optimization problem costed a percent or so on SPEC if you build it with -mcmodel=medany
<sorear> (which forces auipc for data access regardless of PIC/PIE/PDE)
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<ja_02> conchuod have you heard any news on if SpacemiT K1 is getting mainlined soon. i dont want to step on someones shoes if they are.
<conchuod> ja_02: No patches yet. There's a bunch of boards at Rivos and Esmil and smaeul have boards too, but if you want to submit, noone has yet committed to doing anything.
<conchuod> If you want to work on anything for it, be my guest!
<conchuod> Or maybe you are one of the Rivos people, given your name is Jesse...
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<ja_02> yeah i am :)
<ja_02> im the 20yr old goofball spending her freetime writing patches for the kernel
<ja_02> sry about any chaos i cause
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<conchuod> ja_02: Well, fire away with any spacemit k1 stuff. You know where to find me if you run into difficulties.
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<lu_zero> if you do and want early testers poke me as well
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