sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<dramforever[m]> update on the c908 / k230 vector load/store to mmio thing: t-head updated their c908 manual today. it says the memory accessed by vector load/store cannot have SO=1 https://www.xrvm.cn/product/xuantie/4106421598796451840
<dramforever[m]> (SO = 1 is their way of saying "strong ordered according to PMA/Svpbmt/their thing)
<davidlt> oh, it (C908) back on their website
<davidlt> Note the English manual wasn't updated.
<dramforever[m]> doesn't seem to be on https://www.t-head.cn/ for me
<dramforever[m]> caching?
<sorear> TIL there's a c908 manual
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<Revy[m]> EN/CN documents are not synchronized.
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<sorear> How do TLS copy relocations work when the defining DSO uses the local dynamic model? Are they just incompatible?
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<sorear> neat, c908 manual mentions svpbmt and sstc. still using pre-standard pmu :(
<courmisch> is this relevant https://github.com/kendryte/k230_sdk/issues/48 ?
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<Tenkawa> Is anyone currently "leading" any innitiatives to get the Milk-V Mars CM into mainline?
<Tenkawa> I wanted to find out if there are any current source trees and testing state I can take a look at. I have been working with the vendor kernel but I think it will need substantial dts and possibly driver work to fully integrate into mainline (if it isn't being done already)
<Tenkawa> looking in kernel -next I don't see anything obvious
<Esmil> ..which should be in my jh7110 branch
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<mps> when the talk is about milk-v, do anyone know for patches to mainline kernel for pioneer board
<Tenkawa> mps: Heh wish I had that board... still only getting JH7110's atm
<mps> Tenkawa: also I don't have it but Alpine project got it and I'm trying to make mainline kernel for it
<Tenkawa> nod.. I am trying to do as much as I can with the boards as well
<mps> thanks to clandmeter and ikke alpine now have riscv64 bare metal builder which means riscv64 will be officially supported with next stable release, I hope at least
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<Tenkawa> Nice
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<ikke> The builder is not completely stable yet, but we'll see how it holds
<Tenkawa> ikke: I am "trying" to convince my co-designer that works with me on a arm image builder project for Debian/Ubuntu/Devuan based boards to add RISC-V support but I need to get some hardware to him so he can have something to run it against
<Tenkawa> since it would be a fair bit of different code to add
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<unlord> palmer: does binutils objdump show local symbols in the disassembly by default?
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<unlord> Both .L and .L_ prefixes show up with objdump -D
<unlord> ahh, but they do not appear in objdump -t
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<sorear> https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/343#issuecomment-1951416265 relocation sketch for fdpic. no promises when it'll become a PR or a working proof of concept
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