sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
<unlord> palmer: has QEMU applied to be part of GSOC this year? The mentoring organization deadline was Feb 6th
<unlord> oh, nice it looks like the answer is yes: https://wiki.qemu.org/Google_Summer_of_Code_2024
<heat> oh dang, not accepted
<unlord> oh dang indeed
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<unlord> courmisch: does perf work for you on the K230 image with 5.10.4 kernel?
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<courmisch> unlord: didn't try
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<unlord> courmisch: I tried and got a segfault, https://paste.debian.net/hidden/46a43233/
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<unlord> running this under gdb, it is in strlen()
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<unlord> downgrading perf-6.6 to perf-5.10.16 (and patching the ebuild to compile) seems to have fixed it
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<courmisch> To be clear, I am *not* working on getting upstream kernel (or SBI or uboot) or anything else on the K230.
<courmisch> at least not at the moment
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<unlord> courmisch: yeah, that is fine, I am happy with this solution
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<courmisch> there are no ways to get integer absolute value in a single vector instruction, are there?
<sorear> nope, none
<sorear> the bitmanip spec recommends neg + max; compare + masked neg might be faster or slower
<unlord> no sign extension trick?
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<sorear> srai, xor, sub? not sure why you'd do that when you have max
<unlord> good point
<courmisch> well there are many ways to do it with two instructions, sure
<courmisch> but it seems only float supports it in a single instruction
<sorear> fabs is a pseudoinstruction for fsgnjx
<courmisch> yes and?
<sorear> and only works because floats use sign-magnitude representation
<sorear> integer abs would have to be an actual instruction. propose it if you can demonstrate a large enough improvement
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<courmisch> I don't know much about silicon, but adding the sign bit to the value bits does not sound like it would need that much extra, would it? well, it's too late anyway
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<sorear> conceptually it wouldn't be weird as part of the "vector fixed point" instruction package, since a lot of them do additions and subtractions with a layer of muxes at the end
<mps> hm, iiuc u74-mc cpu in JH7110 SoC don't have vector extension. cpufetch says 'Extensions: rv64imafdc_zicntr_zicsr_zifencei_zihpm_zba_zbb'
<courmisch> more accurately, xor each value bit with the sign bit, then add the sign bit, I guess
<sorear> you can do either way
<sorear> the fixed-point pipeline will likely be happier with front-loading the negate rather than waiting for sign bit fanout, then an add later in the cycle
<courmisch> mps: s/iiuc //
<mps> courmisch: so my guess is ok
<sorear> why are we talking about jh7110 in a conversation about vectors
<courmisch> clearly we should be using sign-magnitude instead of that weird two-complements nonsense!! :O
<mps> sorear: sorry, I didn't wanted to disturb and my question is not related to current discussion
<jrtc27> (yes, u74 doesn't have v, even the more recent revisions; don't know why that's a noteworthy thing to mention but your understanding is correct)
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<sorear> « We have already defacto forked from the psABI pretty much everywhere » not sure how scary this should be as a psABI maintainer
<conchuod> I feel like I need to read the whole thread where that quote originates..
<Tenkawa> conchuod: hey got a question about the Milk-V Mars Patches... I've got a CM board sitting here running successfully with 6.8.0-rc5. The only thing I'm having difficulty tacking down is getting the usb to function (waveshare IO board for informational purposes)... Anything obvious about this setup I should know or current known issues? I noticed you submitted a fair number of patches I'm using on it in mainline.
<Tenkawa> s/tacking/tracking
<Tenkawa> Everything else seems to be functioning ok (even NVMe root)
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<conchuod> Tenkawa: I'm sorry, what did I submit patches for that's being used on a jh7110 system?
<Tenkawa> It was delegated to you.. (pending this "is" you..)
<conchuod> Ah you mean it was delegated to me on patchwork.
<Tenkawa> yeah
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<Tenkawa> I didn't notice the delegated until i reread
<conchuod> I haven't authored any patches for the jh7110 stuff, other than cleanups, so I am not too sure. Does the same thing work on a vf2?
<Tenkawa> The vf2 works just fine but its a VL805 vs a Cadence controller
<conchuod> Oh, the mars uses a different usb controller?
<Tenkawa> yes
<conchuod> That seems odd, why would they not use the one on the soc?
<Tenkawa> Not sure
<conchuod> huh, looking at those patches, there's nothing that indicates that it would use a different usb controller
<Tenkawa> Someone tested earlier for me to confirm on another unit since mine is partially functional
<Tenkawa> [M] <S​hadow AI6FS> and then on the host computer dmesg shows as that happens:
<Tenkawa> [2302575.546408] usb 1-3: New USB device strings: Mfr=1, Product=2, SerialNumber=3
<Tenkawa> [2302575.303059] usb 1-3: new high-speed USB device number 14 using xhci_hcd
<Tenkawa> [2302575.546399] usb 1-3: New USB device found, idVendor=0559, idProduct=7110, bcdDevice= 2.00
<Tenkawa> [2302575.546412] usb 1-3: Product: StarFive JH7110 Device
<Tenkawa> [2302575.546415] usb 1-3: Manufacturer: CADENCE
<Tenkawa> [2302575.546418] usb 1-3: SerialNumber: 100000000000
<conchuod> The soc itself supports usb 2 and usb 3
<conchuod> the docs for the device dont suggest more usb controllers
<conchuod> the rpi however does use a vl805
<Tenkawa> conchuod: so does the VF2
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<Tenkawa> root@vf2:~# lspci | grep VL
<Tenkawa> 0000:01:00.0 USB controller: VIA Technologies, Inc. VL805/806 xHCI USB 3.0 Controller (rev 01)
<conchuod> ohh, pci..
<conchuod> of course it wont show up in those patches..
<Tenkawa> yeah it "feels" as it could be as simple as a dts change
<conchuod> Also, I found the schematic for the vf2, which I could not easily for the mars
<mps> on my VF2 lspci '0000:01:00.0 USB controller: VIA Technologies, Inc. VL805/806 xHCI USB 3.0 Controller (rev 01)'
<conchuod> and yes, there is a vl805
<conchuod> PCI support isn't in mainline for the jh7110, are you using mainline or Esmil's tree?
<Tenkawa> conchuod: Esmil's
<conchuod> got a link?
<Tenkawa> on Milk-V currently actually
<Tenkawa> the one Jeff and a few others were
<Tenkawa> yeah.
<Tenkawa> just a sec
<Tenkawa> https://github.com/geerlingguy/sbc-reviews/issues/22 start at "SPL, OpenSBI, and U-Boot"
<Tenkawa> Using as my starting point for the kernel
<Tenkawa> (and OpenSBI/U-Boot)... the root is my own
<Esmil> conchuod: that's to make the kernel work with the u-boot shipped in the spi flash on (early?) VisionFive 2s
<Tenkawa> I've actually been very happy with this new board's performance.. I just want to "de-wire" it lol
<Esmil> ..which didn't reserve space for opensbi
<conchuod> Isn't opensbi meant to reserve space for itself?
<conchuod> Or is this a real world version of "opensbi didnt mark itself as no-map"?
<Esmil> right yeah, so it might be that the opensbi they shipped didn't do that
<conchuod> I might look into it if I have some time, been curious to see if/when this would actually happen.
<conchuod> I had a runtime kernel fix for it, I'll dig it up and maybe you can check.
<Esmil> yeah, i've long overwritten my spi flash with a newer u-boot
<conchuod> Yah same, was one of the first things I did. I think I tested the u-boot patches submissions for it.
<conchuod> Tenkawa: Does the PCI driver probe on the mars at all?
<Tenkawa> Yeah I'm running a nvme on it
<Tenkawa> 0000:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation PS5021-E21 PCIe4 NVMe Controller (DRAM-less) (rev 01)
<Tenkawa> booting directly to it
<conchuod> I'm not really sure then, nothing off the top of my head at the very least.
<Tenkawa> Like I said.. it feels like a missing dts node
<conchuod> That vl805 should be detected at runtime since it is a pci device.
<Tenkawa> I don't think its a vl805
<Tenkawa> why would it be
<conchuod> Right, back to digging for a schematic then.
<Tenkawa> why would there be a cadence in that connection output I pasted earlier
<Tenkawa> thar was from a host connection to a unit
<Tenkawa> er that
<conchuod> There should be on the vf2 also? The jh7110 has a cadence usb 2 and 3 controller
<Tenkawa> how does the vl805 get mapped pre-os?
<Tenkawa> since there is no driver/firmware that I can find... (or is missing)
<conchuod> What do you mean "pre-os"?
<Esmil> Tenkawa: which device tree are you using on the mars board?
<Tenkawa> Esmil: vf2 1.3b
<Esmil> Tenkawa: ah yeah. Jisheng submitted dt patches for the mars board you should really be using, but they're missing the pcie nodes
<Tenkawa> doh
<Tenkawa> I had a feeling
<Esmil> i think i sent you a link to them the other day
<conchuod> That link you posted from Jeff Geerling has a link to them also.
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<Tenkawa> Let me reread (if they weren't in the "main" build section I didn't apply them)
<conchuod> I couldn't find a schematic, I sent them an email.
<Tenkawa> yeah. I think I missed those patches somehow
<Tenkawa> let me pull and verify
<Tenkawa> I got the long list but missed the 2 individual files
<conchuod> Tenkawa: Also, is there a big QFN package with "VLI" on it on the mars? Probably under your nvme drive.
<Tenkawa> Interesting indeed
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<conchuod> IIRC the mars is almost exactly a vf2 copy and this image suggests it does have one: https://milkv.io/assets/images/mars-96a343cc6d7da47a7d429fb3aeda1c0a.webp
<Tenkawa> well it should be.. most of them are..
<conchuod> Whether it is a vl805 or not I cannot tell obviously, but it has something along those lines.
<Tenkawa> Even the Star64 realisticly is with a few tweaks
<Tenkawa> (which I also want to get mine converted one of these days)
<Tenkawa> ok.. lets see if these new dtbs do any better
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<Tenkawa> Well gotta run for now but thanks for all the help. I will be back hopefully with good news after some more testing. Tomorrow will be out due to no time but I plan on taking a look again Sunday I hope. Cheers all
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