<smaeul>
conchuod: yes, I need to do that. thanks for the reminder.
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<geist>
huh that's interesting, got a random machine check on my computer
<geist>
process crashed
<geist>
aaaaand wrong channel
<geist>
alas, was a dirty stinky x86 machine
<geist>
so it deserves it!
<sorear>
counterpoint: all of the stuff that was needed when we pivoted from "pure research ISA" to "open-development commodity ISA" was hella rushed, if we'd _actually_ been developing H and AIA since 2010 they'd be much better
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<conchuod>
sorear: reading this again, what is the actual scope of that config structure spec? In my naivety, I thought it was just for riscv standard/extension related things. I see stuff in here about discoverable buses though, which gives the impression they want to be able to describe a whole system, peripherals etc.
<sorear>
good question, i've got "read everything from tech-config" on my todo list but it's near the bottom
<conchuod>
sorear: The spec is only 1/8 written, it's not too bad.
<sorear>
the answer might be in a working group charter or a google doc somewhere
<conchuod>
I've started writing a mail, but I won't send it til I hear about the PoC.
<conchuod>
If they really intend describing the entire system, I wish them luck.
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<Tenkawa>
davidlt: I was able to get the Mars to boot. I am making the ram dts adjustment patch now to see if that fix works.
<davidlt>
Tenkawa, does it have eeprom to check the information?
<Tenkawa>
It should.. its just another JH7110
<Tenkawa>
Its another relabeled VF2 essentially
<Tenkawa>
ok here goes...
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<sorear>
What profile or other specification guarantees the availability of specific SBI sub-extensions? I just realized that sbi_send_ipi isn't actually mandatory in the SBI specification and I can't find where it is mandatory
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<Tenkawa>
davidlt: appears u-boot is reporting wrong as well
<conchuod>
"The S-Mode IPI (IPI) extension MUST be implemented, if the Incoming MSI Controller (IMSIC) cite: [Aia] is not available."
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<sorear>
I would expect there to be a requirement somewhere that there are at least N MSIs available for use as IPIs in addition to the ones needed for hardware
<sorear>
I hope that once BRS is ratified they won't try to retroactively weaken any other requirements on the basis of other specifications that didn't exist at ratification time
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<geist>
yah, without it all you need is some external hardware that can fire a regular IRQ on a specific cpu
<geist>
i've worked with a board with exactly this situation
<geist>
also without machine based ipis, that also means other things like SBI based TLB shootdown doesnt work, since SBI can't internally do it
<sorear>
conchuod's link clearly indicates that SBI TLB shootdowns (rfence) are not required if IMSIC exists
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<sorear>
you probably wind up needing much of the IPI machinery for the suspend and performance control extensions
* geist
nods
<geist>
I need to read up on imsic. been working with archaic and nonstandard riscv stuff the last year so haven't had much chance to drool over new bits
<sorear>
AIA is something like five unrelated extensions (IMSIC, APLIC, local interrupt prioritization, xvien/xvip, MRIF), two of which are purely memory mapped and three of which have a documented way to provide MSIs
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<sorear>
it's a huge amount of flexibility and I'm dreading whatever the device tree binding is going to look like
<geist>
yah, APLIC I had dug into, hadn't looked at MRIF and IMSIC though
<sorear>
i expect it'll be extremely slow in practice due to the requirement for enabled pending interrupts to take immediately and pipeline flushes whenever you touch anything tangentially interrupt related
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