sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<pakcjo> noob question, what's fpga and its relationship with risc-v?
<xypron> pakcjo: field programmable gate arrays can be used to implement RISC-V processors. Sometimes FPGAs are used alongside RISC-V processors (e.g. as accelerators, to address periphery)
<sorear> a FPGA is a type of parallel computing device, similar in some ways to a GPU but good for different tasks
<pakcjo> oh thanks!
<sorear> one of the things FPGAs are good at is simulating the operation of a microchip, so FPGAs are commonly used by people developing RISC-V microprocessors among other types of microchip
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<drewfustini> bjdooks: i'll be at EOSS Seattle :)
<sorear> is the string section name the only thing that matches an ELF section to its corresponding list of relocations?
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<jrtc27> the relocation section's sh_info has the corresponding section's index
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<sorear> mm
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<sorear> Is the TLSDESC ABI ratified yet? I think we added two entirely unnecessary relocations and we can reclaim the numbers
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