sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<la_mettrie> JH7110's reset drivers perform timeout polling in order to prevent hanging when deasserting reset lines associated to gated clocks. no other reset driver mentions gated clocks. so is this some kind of hardware bug in JH7110 or what?
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