sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<palmer> khem: ya, we did a bunch of TLB refactoring stuff. I'd start by looking at anything in arch/riscv without a fixes/stable tag that got backported, something might have been autoselected
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<dramforever[m]> and I'm like, *very* confused about whether it is allowed that PMLEN > NVBITS
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<dramforever[m]> it seems that the entire spec just keep saying how it is difficult to implement in hardware, but nowhere does the spec actually forbid say PMLEN = 16 in Sv57? does this mean it's actually allowed?
<sorear> it's allowed in the sense that an implementation can choose to provide it, but PMM is a WARL field and so all of its possible values are individually optional to support
<dramforever> I also just realized that PMLEN = 16 for U-mode in Sv57 could work if the S-mode software is like, aware and handles it
<dramforever> okay but hear me out, the spec also says that the pc is *not* masked when fetching instructions
<dramforever> so it's possible to end up with a "forbidden address space" where the pc can reach but load/store instructions can't
<dramforever> so, say you're a hypervisor, and the guest has pc pointed to this forbidden space and does an MMIO load/store that traps to the hypervisor
<sorear> maybe file an issue that HLVX should ignore pointer masking? pointer masking in hypervisors seems fairly useless to begin with
<dramforever> well they just need to set it up in the guest
<dramforever> like the guest is running a JIT'd language or something
<dramforever> okay right, i'm mostly just asking here because i want to be sure i'm not missing something obvious like "actually this never happens"
<sorear> i was under the impression M-mode pointer masking was deleted since there wasn't actually a use case, somewhat concerning if it's still in the newest pdf
<dramforever> wherever it's been deleted it hasn't landed: https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc#smmpm
<dramforever> > Setting PMM enables or disables pointer masking for M mode, according to the values in Table 2.
<dramforever> still there
<dramforever> in mseccfg
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<dramforever> but what i said would still be a problem if the *guest* is allowed to configure pointer masking itself
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<dramforever> anyway thanks to sorear for helping me making sure i'm not completely insane for thinking this is a problem. i filed https://github.com/riscv/riscv-j-extension/issues/63
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