sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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* cousteau is curious about the RoCC instruction format, and the order of the xd/xs1/xs2 bits, and wonders if there was a motivation to put them in that order
<cousteau> I have also found something called the NICE interface, which has its own instruction format, which happens to be identical to that of RoCC, but I've seen no mention on any of them being based on the other...
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<la_mettrie> is jh7110's pll1_out clock supposed to be ever set from kernel drivers? it seems touching that clock (which is connected to DDR controller) halts the system immediately
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<fuwei> ping drewfustini
<drewfustini> fuwei: welcome
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<drewfustini> I believe Esmil th1520 branch is only linux-riscv mailing list patches on top of mainline https://github.com/esmil/linux/commits/th1520/
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<Esmil> drewfustini: that's right, although i've fixed up some of the patches for 6.7 and using the pinctrl driver, but that should be described in the commit messages
<drewfustini> thanks
<fuwei> Esmil: thanks , I will try it today
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<khem> palmer: I am seeing a crash with 6.6.15 on qemurv32 https://snips.sh/f/O9eArhszq4, it works ok with 6.6.12 any suspects ?
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<conchuod> If an actual bisection isn't on the cards, 6.6.13 got quite a few backports to mm-ish stuff in arch code, so it might be worth checking that first to see if the issue is there too.
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<khem> conchuod: hmm ok thanks for info,