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<bjoto>
For some reason the patchwork GH runners is stalled. Looking into it...
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<bjoto>
...and PWCI is up again.
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<scrts>
palmer: I saw SiFive products, but was wondering if there was anything else...
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<courmisch>
sorear: in the case that an extension is missing on some CPUs, the scheduler can always fix it. Kernel devs aren't going to like that, but I don't see any other realistic solution that won't suck
<courmisch>
sorear: for mismatched VL across cores, AFAICT, the kernel will actually HAVE to turn V off except for processes that specifically sign up for whatever the API to handle that mess will be
<bjdooks>
has big.little in arm had the same problem? otherwise something like cpusets to contain processes might be needed
<courmisch>
bjdooks: talking to me?
<courmisch>
bjdooks: AFAIK, bigLITTLE is just different perf characteristics, not different ISAs
<bjdooks>
possibly, although who knows what people do
<courmisch>
the arm64 kernel blacklists any extension that is not available on all CPUs
<courmisch>
(and refuses to boot hotplugged CPUs that don't support extensions that the boot-time CPUs have)
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<conchuod>
The riscv kernel also blacklists extensions that are not available on all cores.
<courmisch>
conchuod: but what about mismatched vector lengths?
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<conchuod>
I forget what was decided there, I do remember talking to Andy about it.
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<conchuod>
I think we decided that != means vector is disabled.
<courmisch>
that would be the safe choice
<courmisch>
but not what would happen if you just parse the DT
<conchuod>
What do you mean?
<courmisch>
the DT will just list "V" not the vector length
<conchuod>
We read VLENB
<courmisch>
well yes
<courmisch>
hence the use of conditional as present unreal
<conchuod>
courmisch: I'm not convinced by looking back at this code though that this is done correctly.
<courmisch>
moving a task from big to small VL is *obviously* broken, but even moving from small to big is subtly broken
<courmisch>
so I don't see any way other than disabling (at least by default)
<conchuod>
Yeah, I am pretty sure that the vlen being different between cores does not result in a correct disabling of vector.
<courmisch>
expanding vector size is broken notably because of the group multipler thing
<conchuod>
At the moment the V bit in the elf hwcap is cleared if vlenb doens't match
<sorear>
but not the hwprobe bit?
<conchuod>
hwprobe just seems to check has_vector().
<courmisch>
would be nice to move task from non-V core to V core, but don't expect anything from me on this other than unhelpful nagging
<conchuod>
Hmm, Andy isn't here.
<courmisch>
didn't SiFive announce a design with a mix of Zvl128b and Zvl512b cores?
<davidlt>
Which one?
<conchuod>
tbh, I'd rather than we had a DT property for vlen than these Zvl things.
<sorear>
are you thinking of sg2380? we don't know much about it
<davidlt>
SG2380 will have P670 and X280, so that's 128 and 512 IIRC.
<davidlt>
I would assume Linux will "ignore" X280 clusters.
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<davidlt>
SiFive offers Mix+Match technology
<courmisch>
vendor kernel might just expose the small vector cores to Linux and put an RTOS on the big vector cores
<courmisch>
kinda like Canaan already did with K230
<courmisch>
but I'd hope that it'd be possible to just run Linux on the big cores and turn the small cores off
<conchuod>
I'll send andy a mail about the vlenb stuff.
<conchuod>
s/vlenb/vlen/
<davidlt>
The current designs (StarFive and SiFive boards) are 5-core IIRC.
<bjdooks>
the fu740 is 4 linux cores and opensbi I think on the small one
<davidlt>
To my knowledge (I might be wrong) that smaller core never gets used
<courmisch>
current meaning JH7110 ?
<conchuod>
polarfire soc is 1+4 too, and we just run firmware on the e51
<sorear>
courmisch: the big vector cores are in-order and likely have significantly worse scalar performance, so it's not a straightforward p/e split
<davidlt>
I assume SG2380 simply will disable X280 cores (yet those are probably Linux capable).
<sorear>
courmisch: i'm also cautious we may see something like ET-SoC-1 where the big vector cores are NOMMU
<courmisch>
eww
<davidlt>
I don't recall details but isn't ET chips more like a GPU?
<sorear>
I think they're both intended to be used in that sort of way, but we don't know anything about the programming interface for either
<courmisch>
wait, a company pitching CPUs for GPU rather than NPU? it can't be
<courmisch>
or is it that they forgot to implement Zvfh?
<courmisch>
</sarcasm>
<sorear>
gpu, npu, it's the same to me
<sorear>
maybe if i actually understood drm+mesa i'd be able to make a nuanced distinction
<courmisch>
AFAIK, GPUs use mostly single precision, while NPUs do half or less
<davidlt>
it's just marketing names
<davidlt>
Intel stuff incl. VPUs :)
<davidlt>
big.LITTLE, P/E, Mix+Match, AMD has "C" cores.
<davidlt>
They all need a different name for marketing reasons
<courmisch>
uh, when I working at a certain green logo GPU company that I won't name, when they were preparing the first gens of "AI" chips, it really was about adding half precision
<sorear>
i think IEEE float of any size is a recent phenomenon on GPUs and they used to have weird vendor-specific types with sizes like 24 bits
<courmisch>
I think they need standard-ish sizes at least since "GPGPU"
<courmisch>
most likely they don't do the weird corner cases though
<davidlt>
incl. bfloat16, int4, and whatever else these days
<davidlt>
Esperanto original IP predates AI/ML boom, but most likely they have what's needed (or will have ASAP).
<davidlt>
Especially as their are marketing it for LLMs.
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<conchuod>
Hopefully Andy can take a look and explain where I am wrong :)
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<sami>
khem: Thanks, I'll take a look. I can see the journald failures with your base 6.6 kernel.
<khem>
sami: ok, I think the Image I includes reverts the patch, so journalctl should work with that image but if you build your own with the given defconfig then you will see it fail
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<sami>
khem: Yes, it works with the kernel image you provided.
<khem>
sami: cool
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<khem>
I spent long time bisecting it :)
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