_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tnt> What would be the "canonical" way of creating a GPIO block with only a subset of the subsignals of a resource ?
<tnt> Mmm ... even the full resource doesn't work. Am I missing something obvious here ?
<_florent_> tnt: you could do something like this
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<_florent_> If this is not covering what you want to do, can you share a bit more info?
<tnt> That doesn't work with GPIOTristate.
<tpb> Title: ("adrv9009_ctl", 1, Subsignal("reset_n", Pins("AH18")), - Pastebin.com (at pastebin.com)
<tnt> This is what I defined. (previously I had them all in one resource, but I split them now since that seemed easier).
<tnt> Really ATM all I needs are the ctl signals and they're outputs, but I'd like to be able to tristate them. (No need for input) and AFAICT I need GPIOTristate for that.
<tnt> So I just tried : setattr(self.submodules, f'adrv{i:d}_ctl', GPIOTristate(platform.request("adrv9009_ctl", i)))
<tnt> (setattr because it's in a loop).
<tnt> (If I use the same syntax and GPIOOut, that works, so it's a bit counter-intuitive that just replacing 'Out' with 'Tristate' dosn't work)
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<_florent_> tnt: can you try this? https://github.com/enjoy-digital/litex/pull/1117
<_florent_> (I just tested verilog generation but not compilation)
<tnt> _florent_: Thanks. Yeah, at least it builds and the verilog looks correct here as well.
<tnt> Arf nm ... ERROR: [Synth 8-2715] syntax error
<_florent_> ok, I look at this
<tnt> assign {adrv9009_ctl0_rx2_enable, adrv9009_ctl0_rx1_enable, adrv9009_ctl0_tx2_enable, adrv9009_ctl0_tx1_enable, adrv9009_ctl0_test, adrv9009_ctl0_reset_n}[0] = main_gpiotristate0_tstriple0_oe ? main_gpiotristate0_tstriple0_o : 1'bz;
<tnt> I thought that was valid TBH but apparently {} can't be a LHS.
<_florent_> tnt: I also have doubts on this when looking at the verilog :)
<tnt> or rather it's the {...}[] that it doesn't like.
<tnt> _florent_: indeed, verilog looks much more sane :)
<tnt> and synth passed.
<_florent_> ok good
<tnt> Tx.
<_florent_> I'll merge it then
<tnt> I'm not sure if it's the "right way" to expose those signals in a single resource or if I'm supposed to set them as independent signals ?
<tnt> (Trying to fit the litex way of doing things).
<_florent_> I generally also put them in a single resource (but without the tristate)
<_florent_> tnt: here is an example for the LiteJESD204B integration: https://gist.github.com/enjoy-digital/cd9ea52fafaebe016e739a90983eb237 This is not a full example but should help you doing the integration.
<tnt> _florent_: Oh, very nice. I'll dig into that tomorrow.
<tnt> I had seen some code from artiq on m-labs but it seems based on some old version of the jesd core.
<_florent_> yes it's not up to date was also only TX, not for SDR. The one I just shared is up to date and TX + RX and used on a SDR system.
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<tnt> Mmmm, Am I blind ? Where's the driver code for the SPIMaster() core ?
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<tnt> nm, looks like you just write to the CSR directly, no wrapper provided.
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<tpb> Title: Artix-7 FPGA Development Board - Digilent Arty A7 - Xilinx (at digilent.com)
<futarisIRCcloud> Shame that the shipping to Australia is just as much as the board
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<bjonnh> $30 more for the USB cable :D
<bjonnh> I may just order that one, I'm still waiting on my ULX3S
<bjonnh> Is it complicated to deal with that ARM on the Zynq-7000?
<bjonnh> lets say I just want to do FPGA for now, but may be happy to have some Arm later
<tnt> with jtag you can configure the fpga and completely ignore the ARM part.
<bjonnh> neat
<tnt> (that's what I'm doing now on a UltraScale+ Zynq :)
<bjonnh> I'll need to find a Jtag cable, they sell them for the same price as the board :D
<trabucayre> cable is onboard
<trabucayre> you have just fo find an usb cable :)
<bjonnh> <3
<trabucayre> JTAG interface is onboard
<trabucayre> FT2232 (one interface for JTAG, second for UART)
<bjonnh> "Briefly describe the reasons you chose Digilent for your purchase today." "Because your board works with Opensource toolchains #litex"
<bjonnh> I'm sure they will be happy about that
<trabucayre> you can you use linux (on PS side) to communicate with the LiteX gateware into PL too
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<bjonnh> My experience with FPGAs stopped at making leds blink on a Fomu, so I'll go slowly :D
<trabucayre> try to communicate with LedChaser :)
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<jeffdi> (venv) jeffs-mbp:verilog jeffdi$ make VexRiscv_MinDebug_Cache.v
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<jeffdi> Hello - I’m trying to build a version of the VexRiscv min+debug core with a small amount of cache (e.g. 64 bytes).  I’ve installed scala and sbt on a Mac via Brew, but getting errors running the make targets in pythondata-cpu-vexriscv.  any suggestions?
<jeffdi> WARNING: A terminally deprecated method in java.lang.System has been called
<jeffdi> sbt compile "runMain vexriscv.GenCoreDefault -d --iCacheSize 64 --dCacheSize 0 --mulDiv false --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_MinDebug_Cache"
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<zyp> that warning looks like it can be ignored, which errors are you getting?
<mithro> I ordered 20 of the Digilent Arty A7 35T boards :-)
<mithro> jeffdi: Can you provide a link to the complete output?
<bjonnh> mithro: are you stockpiling ?
<mithro> tcal: Has a lot of experience with sbt and LiteX thanks to his work on the CFU playgournd (http://cfu-playground.rtfd.io/)
<mithro> bjonnh: I send them out to people who contribute to my projects
<tcal> jeffdi: yes, especially the first time you run the build, there are lots of warning that can be ignored. I don't recall seeing that one...I recall ones about duplicate main methods.
<jeffdi> tcal: reposting using gist. not sure what else to provide https://gist.github.com/jeffdi/8dbc17a777492bff039951985a803c0f
<tcal> jeffdi: is the ./ext/VexRiscv/ submodule loaded? What do you see in that directory?
<jeffdi> tcal: just posted the output from find ext -print
<tcal> In the verilog/ directory with the `Makefile` that you're using, there should be an ext/ directory, and VexRiscv inside that, unless things are completely different with mac development.
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<jeffdi> tcal: yes, there is
<tcal> jeffdi: FYI if we can't get to the bottom of this before I need to run, try asking at https://gitter.im/SpinalHDL/VexRiscv (you can log in with your github credentials) . @Dolu1990 is the creator of VexRiscv.
<tpb> Title: SpinalHDL/VexRiscv - Gitter (at gitter.im)
<tcal> jeffdi: What's inside the directory? Something like this?
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<bjonnh> mithro: great so that's an even better discount than the digilent one!
<tcal> jeffdi: dolu1990 is in Europe so you probably won't get a reply until tomorrow.
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<cr1901> Is Dolu1990 on the slack side of the bridge?
<cr1901> Wait, wrong channel lol
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<tcal> Oh, that might be your issue. Run `git submodule`. Also, `cd` into `ext/VexRiscv` and run `git remote -v`. If the submodule is loaded correctly, for the latter command, you'll see:
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<tcal> jeffdi: If the submodule is not loaded correctly, then first you have to recursively delete `target/` in `ext/VexRiscv`, and then run `git submodule update --init --recursive` while sitting in the `verilog/` directory above.
<jeffdi> tcal: thank you!! i think that did it! its running now...
<tcal> 👍