Hey everyone, quick question about block diagrams and litex cores. I would like to integrate the litepcie core into my design so that I can upload my design via pcie. Is there a way to generate a block diagram of my design that I can then import to vivado and integrate with my verilog design? if not, is there a way to output a verilog version of the litepcie design so that I can accomplish the same task without the block design
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_florent_, I tried to use litex_term as it is, but serialboot's writes are not aligned so I had to modify it, and boot.c and other files. Now it can serialflash (if code is not executed from flash of course) but it breaks compatibility with actual litex_term.
I'm not sure if it's usefull to anyone
And litex_termm send the size of payload as a byte, so either you add 1 somewhere to the size and you won't be able to send frames with payload = 0, or you won't be able to send payloads of 256 bytes.
So, may be it's time to break litex_term a bit and fix all those bugs (we could probably keep compatibility with different magic numbers to detect different versions).
acathla: This features has been contributed in the past, but I removed it since was not easy to maintain and not really used. For flashing, I have a preference to have use external tools (OpenFPGALoader, OpenOCD) or a proper DFU bootloader (ex Foboot) and I'm not sure this should be part of the BIOS.
florent, is there a way to generate a block design or output a verilog version of litepcie so that I can give my custom verilog design the ability to be uploaded via PCIe?
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_florent_, ok, i'll keep a patch for my own use then