peepsalot has quit [Read error: Connection reset by peer]
peepsalot has joined #litex
Degi_ has joined #litex
Degi has quit [Ping timeout: 260 seconds]
Degi_ is now known as Degi
toshywoshy has quit [Read error: Connection reset by peer]
toshywoshy has joined #litex
lexano has quit [Ping timeout: 260 seconds]
lexano has joined #litex
FabM has joined #litex
FabM has quit [Changing host]
FabM has joined #litex
pavelow_ has joined #litex
pavelow has quit [Ping timeout: 246 seconds]
jersey99: actually, I tried to reproduce my issue with the failing ARP and UDP port today and, with all of the patches included it just works now! Even the ARP requests (which used to cause trouble with UDP but not with ICMP, that was always a bit odd)
It's really important to pass dw=64 everywhere though. Maybe that could be the issue?
leons I really only have 1 place to pass the dw, for the UDPIPCore, and that looks good. I have a few questions regarding the udp user_port interface now: 1. The length is still in bytes, correct? 2. Is the last_be now expected to be asserted?
I think the length is still in bytes, yes. And you should assert last_be, but only when last is also asserted. For all other bus words last_be should be 0
Thanks, all as expected!
jersey99: right, for the LiteEthUDPIPCore there's only a single dw parameter. I had previously instantiated the different components myself and messed up the dws 🙂
RaYmAn has quit [Remote host closed the connection]
RaYmAn has joined #litex
leons and _florent_ The branch works on KC705 for me now. I didn't test it at line rate, but I get the data that I push on the UDP port, onwards!
That's really awesome
It probably doesn't work at line rate, there's still some delays created by for instance the preamble inserter (1 clock cycle between packets) and the ARP table lookup also takes some cycles even if the cache is hot. I'll work on this further in the coming days/weeks. Appreciate any support!
somlo: yes, I replaced linux-on-litex-vexriscv/images/Image by a symlink to arch/riscv/boot/Image in my linux-riscv-orangecrab build dir
somlo: btw, I guess current litex-rebase doesn't build for vexriscv, and you need to apply the patch for irq-litex-vexriscv I emailed you? ;-)
jersey99: can you by chance share how you instantiate the 10G PCS/PMA core? I think I know where I went wrong, I was trying to get the ten_gig_eth_pcs_pma instantiated on UltraScale+, but that platform is unsupported by that core. I suspect your using the xxv_ethernet core instead which supersedes it (called 10G/25G High Speed Ethernet)?