<yootis>
_florent_: just a heads up, but building docs won't work on systems with Python 10 (like Fedora 35). The problem is in either sphinxcontrib-wavedrom or wavedrom. Some python imports moved around and/or they are using a deprecated feature that finally went away.
<tpw_rules>
do you mean 3.10?
<yootis>
sorry, python 3.10
<yootis>
Python 10 would be awesome, though :)
<yootis>
Maybe by Python 10 they'll get rid of the GIL...
<tpw_rules>
:D
essele has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
Degi has quit [Ping timeout: 240 seconds]
Degi has joined #litex
<sajattack[m]>
I don't want 7 more breaking releases of python
<sajattack[m]>
the way they handled the 2-to-3 transition was horrid
<_florent_>
yootis: I'm going to build a machine for CI hardware tests to catch this more easily in the next months with several boards integrated (PCIe ones: ex Acorn, BCU1525, etc...) or connected (ex: Arty, Butterstick, Fomu, etc...).
<mntmn>
_florent_: i've set up my litex framebuffer to eDP pipeline with 2 external bridge chips in linux-on-litex-vexriscv, but i've run into a problem. drm crashes with "Unable to handle kernel access to user memory without uaccess routines". do i have to turn this on somewhere?
<mntmn>
i see that uaccess.S exists in arch/riscv/lib, but not sure if that's not enabled or something
<mntmn>
hmm, looks like this is included if CONFIG_MMU=y, which is def. y
nelgau_ has quit [Remote host closed the connection]
nelgau has quit [Ping timeout: 256 seconds]
zjason`` has joined #litex
zjason` has quit [Ping timeout: 268 seconds]
nelgau_ has joined #litex
nelgau_ has quit [Remote host closed the connection]
<nickoe>
I wonder what this reall means ... "ValueError: ('Could not lower all specials', {<migen.fhdl.specials.Instance object at 0x7f8ac2fb6e00>})" Trying to use platform.add_source to add a verilog module, then the Instance of it and then add that instance to self.specials...
<nickoe>
sajattack[m]: Wasn't it more about library maintainers not prioritizing making their module compatible with both in the transition period that sorta "killed it"?
nelgau has joined #litex
<nickoe>
I am trying to simulate part of my design with SimPlatform without a COU, ask without SocCore. So maybe I need that somehow?
nelgau has quit [Ping timeout: 245 seconds]
<sajattack[m]>
<nickoe> "sajattack: Wasn't it more..." <- It was about making a hard split in the language and not maintaining backwards compatibility. Whether maintainers responded well to having to make changes is irrelevant. The lang maintainers should have provided a smoother transition, like Rust does with "editions"
<tpb>
Title: What are editions? - The Edition Guide (at doc.rust-lang.org)
<sajattack[m]>
* It was about making a hard split in the language and not maintaining backwards compatibility. Whether library maintainers responded well to having to make changes is irrelevant. The lang maintainers should have provided a smoother transition, like Rust does with "editions"
Martoni has joined #litex
<nickoe>
ok
<nickoe>
Can't one use a migen test bench with a litex soc?
Martoni has quit [Ping timeout: 240 seconds]
<nickoe>
I don't get why I get termios.error: (25, 'Inappropriate ioctl for device') with the SoCMini
<nickoe>
as my BenchSoC
<nickoe>
Mm, I cam not sure I understand how I can make a CPU-less simulation with the MiniSoC and make a testbench for some modules in it.
<nickoe>
*SoCMini that is.
<nickoe>
mm, I see that run_simulation is used in test_adaptaion in litedram..
<nickoe>
is it possible to make a test bench which can run use Instance of some verilog module with litex? It appears to me I can only run a "normal" simulation and not write a migen test bench and use run_simulation to use the testbench