sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
<muurkha> huh, that's interesting, I hadn't heard of those. the cheapest i'd seen were some iCE40s
<muurkha> the smallest of which are I think 600-some 4-0LUTs
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<bjdooks> right, that's the major panic of fogetting to Japan pre-entry registration sorted
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<AmyMalik> ¿
<muurkha> !
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* GenTooMan forces everyones riscv system to do a division by 0.
<AmyMalik> why?
<GenTooMan> just to be silly.
<muurkha> glad to see you've closed your open ¿?
<muurkha> division by zero is always controversial because there's no good way to handle it, so people disagree about which way is least bad
<muurkha> you might even say...
<muurkha> IT
<muurkha> IS
<muurkha> DIVISIVE
<GenTooMan> that was pun intensive.
<GenTooMan> well it is important to handle operations that are problematic. I wonder what the IEEE standard for floating point recommends.
<muurkha> Inf
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<muurkha> this has the utterly hilarious consequence, if you are a troll, that -0 == +0 but 1/-0 != 1/+0
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<muurkha> because 1/-0 is, naturally, -Inf
<muurkha> arguably this is better than RISC-V integer division where 1/-0 == 1/+0 == -1 (if interpreted as signed, anyway)
<muurkha> some other architectures trap instead
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<GenTooMan> I prefer the trap to be honest.
<GenTooMan> although if you can't return to where the execution is / was that might be troblematic
<jrtc27> microarchitects don't like arithmetic instructions that can trap
<muurkha> it's probably not much of an exaggeration to say "microarchitects don't like instructions that can trap"
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