sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<conchuod> prabhakarlad: >Tested all the IP blocks on RZ/Five which use DMA
<conchuod> Sick, it all works?
<prabhakarlad> conchuod: Yes it all works good ;). Just that a bit slower compared to a similar ARM64 SoC which has cache coherence port!
<conchuod> How is it perf wise compared to your old way before we all started yelling about errata?
<conchuod> the same I would assume?
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<prabhakarlad> Yes performance is the same as the previous one, so no harm using the errata option!
<conchuod> Cool :)
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