sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<dh`> here's your vector, victor
<Ellenor> eep.
<pabs3> palmer, drewfustini: the RISC-V space needs to learn NDAs suck :)
<Ellenor> the legal system as exists would need to be obsoleted
<drewfustini> Yeah, the trouble is a lot of the RISC-V vendors so far don't have much of their own IP. So most of the SoCs have lots of licensed IP in them. It is definitely annoying in terms of driver development
<drewfustini> Driver development done by open source community, I mean
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<pabs3> a less widely-scoped NDA might be a solution in that situation
<drewfustini> These smaller SoC vendors don't often get the leverage to convince the IP companies to allow them to include real register level documentation
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<drewfustini> Yeah, these SoC vendors need to do better job negotiating about what documentation they can release to open source software developers
<palmer> and/or any need to do so: if you're just selling into the embedded market then anything upstream is an afterthought, you just throw together an SDK and ship it
<drewfustini> Yeah, in fact, many SoC vendors I've worked with never even considered public documentation.
<drewfustini> That's why I do appreciate vendors like TI and NXP that have real technical reference manuals for their SoCs.
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<bjdooks> jrtc27: because no-one implements theur phy wrappers the same way...
<bjdooks> jrtc27: the core is fairly standard, the issue is resoruces needed to get the vendor-phy and whatever platform resets/power/etc going
<bjdooks> the wrappers don't tend to be huge, but it is mostly things like phy init
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<bjdooks> the one i did for qemu is very simple
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<mps> rneese: I booted visionfive v1 with uefi, kernel start but got it stuck with message 'pinctrl-starfive 11910000.pinctrl: error -ENOENT: could not get reset'
<mps> same kernel boots fine with u-boot extlinux.conf, i.e. without uefi
<Esmil> mps: you need to load the dtb that was generated with the kernel you built
<Esmil> ..with uefi you'll normally need grub or systemd-boot to do that before executing the kernel
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<mps> Esmil: yes, I'm using grub, and right now searching how to load dtb
<Esmil> devicetree <path to dtb>
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<mps> Esmil: in grub? does it work
<Esmil> yes
<mps> ok, will try now
<mps> I thought u-boot will load dtb
<Esmil> mps: it can, but u-boot doesn't know which kernel you choose in grub, so won't know which is the right dtb to load
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<mps> Esmil: 'my' grub doesn't work with devicetree param
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<Esmil> mps: oh, i guess you need to update it then
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<mps> from grub cli I can do 'devicetree /boot/dtbs-starfive/starfive/jh7100-starfive-visionfive-v1.dtb' but same option in grub.cfg doesn't work
<Esmil> hmm.. you need the devicetree stanza besides each linux stanza
<mps> yes, I added it there
<Esmil> ok that's all i know about grub
<mps> also I don't know much
<mps> because this trying to load dtb with u-boot
<mps> ofc, it works fine with u-boot and extlinux.conf
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<rneese> mps you can learn from out builder
<mps> rneese: could you point me to it
<mps> ah, thanks
<rneese> look at extensions/grub-riscv64.sh
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<mps> yes, u-boot loads dtb fine, and then grub boots boards fine
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<rneese> glad you got it working
<rneese> now just build it into your script
<mps> rneese: actuall problem is u-boot mmcpart variable, default is 0:3 but uEnv.txt is on 0:2
<mps> so have to add one fake partition
<Esmil> mps: with sfdisk you can add arbitrary partition numberss
<mps> Esmil: yes, I know, but trying to not use sfdisk
<mps> I have old script with parted which 'hack' this
<mps> and I can't understand why starfive set default mmcpart to 0:3
<mps> ofc, I can change it in u-boot and save to flash, but for now want to use factory setup for users to not hassle with this
<mps> ikke: do you have your board handy to check what is default mmcpart variable in u-boot (so we could have uefi with alpine, and grub)
<ikke> I'd need to reconnect it
<mps> no hurries, when you find time
<rneese> but the file hellped and hope you get yours working
<mps> rneese: yes, you 'forced' me to try again with my script
<rneese> forced you I did not hold a gun at your head
<rneese> geeze
<ikke> s/forced/encouraged
<rneese> lol ok
<rneese> goodluck
<rneese> just means youo will be branching out
<rneese> while you pine away
<mps> rneese: well, right, encouraged to look and test again
<mps> I'm self taught in english and looks like I'm not good teacher (have problem to find proper words)
<rneese> no problem
<mps> rneese: and ofc, thank you for the help
<rneese> < english is my 2nd lang . English Sign is my first
<rneese> so I know how it is
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<muurkha> looking at https://www.cnx-software.com/2022/11/02/sifive-p670-and-p470-risc-v-processors-add-risc-v-vector-extensions/ I want to ask: how good is compiler support for the V extension at this point?
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<another|> the more important question is: how good is kernel support?
<palmer> there's no support in Linux, GCC, or glibc. LLVM can generate V code, but it's super early and there's still lots of work going on.
<muurkha> palmer: thanks!
<muurkha> another|: I feel like kernel support is something you can add in an afternoon though
<muurkha> but maybe I'm underestimating it?
<muurkha> also you can use it without a kernel; lots of people don't run kernels on their GPUs and DSPs
<another|> that's cool and all but I want to write asm for linux
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<muurkha> it's a pastime I frequently enjoy myself
<another|> and the latest patchset I could find [0] is a pain to apply. [0] https://patchwork.kernel.org/project/linux-riscv/cover/cover.1652257230.git.greentime.hu@sifive.com/
<bjdooks> another|: which kernel to? i go it to go onto v5.17.7 ok
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<bjdooks> it does need sorting out
<muurkha> palmer: none of them support the Allwinner D1's quasi-V either, do they? iirc jrtc27 telling me Allwinner went with an incompatible pre-standardization variant
<palmer> "incompatible" is up to the vendor ;)
<another|> bjdooks: was trying with 6. should probably go lower
<mps> ikke: I made POC script to build alpine boot image with uefi and grub here https://tpaste.us/DBna
<bjdooks> might be worth proding again to see if it v11
<tusko> hot
<conchuod> There's a v12, that "should" apply more easily to mainline: https://lore.kernel.org/linux-riscv/20220921214439.1491510-1-stillson@rivosinc.com/
<muurkha> palmer: are you saying that the Allwinner D1 has vector support that might or might not be compliant with the ratified V spec, depending on the vendor? The vendor of what, the board, the OS?
<palmer> vendors decide if their implementations are compliant with the spec, the T-Head marketing material says it is
<conchuod> They're compatible if they say they are :)
<muurkha> oh, I see, thanks!
<palmer> it's the same as their page table bits
<muurkha> what's the deal with their page table bits?
<conchuod> In other news, my dog is also vector capable.
<muurkha> how many gigaflops is your dog?
<conchuod> 2, one per ear
<muurkha> those are some very floppy ears!
<another|> conchuod: heh. I even had that open in a tab
<conchuod> It's basically the same as v10, but you;ll likely have an easier time applying it
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<palmer> arnd: do you want me to just send that SOC email to the lists?
<arnd> palmer: yes, that's fine
<palmer> OK, I'll post it in a bit -- I'm still kind of buried in the profile craziness ;)
<conchuod> if someone says they're compliant with a profile, are they?
* muurkha complies with all the profiles
<conchuod> IK that sounds like a joking comment, but I'm actually curious.
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<palmer> they are as far as I'm concerned, and it's kind of a moot point because they can just say they're compatible with every extension and thus are compatible with the profile
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<palmer> obviously that's a mess, but I don't see any way around it from SW land
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<muurkha> they probably won't be compatible as far as you're concerned once you're debugging software running on them; at that point you will care more about what the chip actually does than what the vendor says about it
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<palmer> ya, there's no way around having to make it actually work. This is all just marketing stuff
<conchuod> Yeah, that's about the same conclusion as I came to Palmer.
<palmer> yep
<conchuod> Hopefully there's less silly business as time goes on..
<palmer> IMO there's going to be way more ;)
<conchuod> Right now we have N vendors and N non-coherent DMA implementations ;)
<palmer> more than that, SiFive has 2 schemes!
<conchuod> ...
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